Can someone at Freescale verify this documentation?
| Data Sheet or Document Name: | i.MX53 Multimedia Applications Processor Reference Manual |
| Revision #: | 2, 12/2011 |
| Page #: | 3141 |
| Section/Figure/Table: | IPU_DI0_GENERAL field descriptions |
| Severity: | Critical |
| Subject: | LCD display clock polarity |
| Description: | The reference manual says:
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17 di0_polarity_disp_clk
DI0 Output Clock's polarity
This bits define the polarity of the DI0's clock.
1 The output clock is active high
0 The output clock is active low
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The i.MX53xD Applications Processors for Consumer Products, Rev. 4.1 datasheet says:
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IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected).
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However, the reference manual does not explain what is high polarity or low polarity.
Please clarify. |
