Current leakage on i.MX7D before power on sequence

[brucetsai]

The customer system is dual board design.

A board is Other brand CPU+OSC

B board is i.MX7D+XTAL

They shared A board's OSC clock channel to i.MX7D external clock input.

 The configuration in kernel: SD1_DATA1 => CCM_EXT_CLK2

But the power time slot of A board is earlier than B board.

So SD1_DATA1 has clock input from A board OSC before i.MX7D start its power on sequence.

It causes current leakage into the other two pins(NVCC_SD1 & VLDO3_3V3).

Signal of SD1_DATA1 (Red)

Signal of NVCC_SD1(Blue)

Signal of VLDO3_3V3(Green)

The customer would like to know what is the side effect under this condition.

By the way,we get information from i.MX6 datasheet about current leakage of power on sequence.

But we can't catch any information like this on i.MX7D datasheet.

Is there any version difference on it?

[Yuri]

Hello,

   Section 4.1.11 (Power supplies usage) of the i.MX7 Datasheet (IMX7DCEC,
Rev. 5, 07/2017) states: "I/O pins should not be externally driven while the I/O
power supply for the pin (NVCC_xxx) is OFF. This can cause internal latch-up
and malfunctions due to reverse current flows."

Have a great day,
Yuri

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