Hi torus1000
one can try to check if this is caused by FEC FIFO overrun issue,
that is FEC DMA cannot access ddr in time:
1, Prioritize the master via M4IF.
Increase FEC priority:
0x63fd_8044=0x33
0x63fd_8048=0x1901a3
2, Increase FEC RX FIFO size.
RX FIFO size = 1.5*(orginal size) => 0x63fe_c150=0x480
RX FIFO size = 1.625*(orginal size) => 0x63fe_c150=0x460
The result as below table, and the patch as below.
Kernel Patch:
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -1300,6 +1300,11 @@ fec_restart(struct net_device *dev, int duplex)
writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
#endif
+ /* Set RX FIFO */
+#ifdef CONFIG_ARCH_MX53
+ writel(0x480, fep->hwp + FEC_R_FSTART);
+#endif
+
/* Set maximum receive buffer size. */
writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
Uboot patch:
--- a/board/freescale/mx53_smd/lowlevel_init.S
+++ b/board/freescale/mx53_smd/lowlevel_init.S
@@ -81,6 +81,17 @@
beq 1b
.endm
+/* M4IF setup */
+.macro init_m4if
+ ldr r0, =M4IF_BASE_ADDR
+
+ ldr r1, =0x33
+ str r1, [r0, #0x44]
+
+ ldr r1, =0x001901A3
+ str r1, [r0, #0x48]
+.endm /* init_m4if */
+
.macro init_clock
ldr r0, =ROM_SI_REV
ldr r1, [r0]
@@ -218,6 +229,8 @@ lowlevel_init:
init_l2cc
init_aips
+
+ init_m4if
init_clock
Best regards
igor
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