Clock sources for timers (i.MX6Q SDP)

[jotes]

Hello everyone!

I have 2 questions related to clock sources on i.MX6Q SDP. I'm using L3.0.35_4.0.0_130424, CPU frequency is 996 MHz.

1) What is the frequency of the ARM private timer's clock? Is it IPG_CLK_ROOT, ½ of ARM_CLK_ROOT, or maybe something else?

2) How to set the clock input source for EPIT to ipq_clk (Peripheral clock)? According to i.MX 6Dual/6Quad Applications Processor Reference Manual it should be done by setting bit 24 in EPITx_CR register. But as I observed, EPIT starts only when CLKSRC is set to Low-frequency reference clock (bits 24 and 25 are set).

Thanks!

[AnsonHuang]

I am confused. Did you use our BSP code? I still suspect you have WAIT mode enabled and sometimes ARM clock is disabled so you get wrong freq. if you are using freescale linux BSP, you can try adding "enable_wait_mode=off" to uboot command line.

[jotes]

You were right, after adding "enable_wait_mode=off" arm_clk_root is equal 400 MHz.

Thank you very much! You helped me a lot!

[AnsonHuang · Accepted solution]

Hi, Jotes

     1. ARM's private timer's freq is 1/2 of ARM freq, we call it local timer.

     2. Programme 2b'01 to EPITx_CR bit 24-25 is to set its clock source to ipg clock, then you should set bit 0 of EPITx_CR to enable EPIT, and you also need to make sure its clock gate is ungated, via setting CCM_CCGR1_CG6 to 2'b11, then you will see EPIT start counting down from 0xffffffff. I tried setting CCM_CCGR1_CG6, then write 0x1000001 to EPIT1_CR, I can see it is running, and its freq is 66MHz, which is IPG's freq. I think you didn't enable its clock in CCM_CCGR1_CG6, please try it.

[Yuri]

Please use the Platform SDK, take a look at  Chapter 8 (Configuring the EPIT Driver) of "iMX6_Firmware_Guide.pdf"

in SDK docs.

https://www.freescale.com/webapp/Download?colCode=i.MX6_PLATFORM_SDK&location=null&fpsp=1&WT_TYPE=La...

i.MX6Q Product Summary Page