CK_FTx_DCC bit value of MMDCn_MPDCCR register

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

CK_FTx_DCC bit value of MMDCn_MPDCCR register

ソリューションへジャンプ
1,560件の閲覧回数
takayuki_ishii
Contributor IV

Hello community,

From rev.1 to rev.2 of Reference manual of i.MX6DP/QP, it was changed CK_FT0_DCC=100 bit setting

from "100 51.5% low 48.5% high" to "Reserved".

But Engineering Bulletin EB828(MMDC & NoC Configuration for Optimal DDR3 Performance on the i.MX 6DualPlus/6QuadPlus) not changed yet.

And Table 3.of EB828, it say that CK_FT0_DCC=100 setting is a recommended settings.

Q.1) Does it have an update of recommended setting of each CK_FTx_DCC?

Q.2) If CK_FTx_DCC=100 setting used, what happen? no effect 50%duty cycle default value?

       or it must change some other setting?

Best regards,

Ishii.

ラベル(3)
タグ(1)
0 件の賞賛
返信
1 解決策
1,416件の閲覧回数
igorpadykov
NXP Employee
NXP Employee

Hi Ishii

I asked internally and got answer below from internal team:

---------------------

Please follow the Engineering bulletin documents for the bit settings as it seems that Reference Manual requires the update for i.MX6DP/QP.

--------------------

Best regards
igor

元の投稿で解決策を見る

0 件の賞賛
返信
6 返答(返信)
1,416件の閲覧回数
igorpadykov
NXP Employee
NXP Employee

Hi Ishii

I will check internally and update.

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 件の賞賛
返信
1,416件の閲覧回数
takayuki_ishii
Contributor IV

Hello Igor,

Thank you for your supports.

I am looking forward to hearing from you.

Best regards,

Ishii.

0 件の賞賛
返信
1,417件の閲覧回数
igorpadykov
NXP Employee
NXP Employee

Hi Ishii

I asked internally and got answer below from internal team:

---------------------

Please follow the Engineering bulletin documents for the bit settings as it seems that Reference Manual requires the update for i.MX6DP/QP.

--------------------

Best regards
igor

0 件の賞賛
返信
1,416件の閲覧回数
takayuki_ishii
Contributor IV

Hello Igor,

Thank you for your information.

I understand that Engineering bulletin documents is oldest information in chronological order, but correct information.

Engineering bulletin   : EB828 Rev. 0, 08/2016             : 100b Increase by 1.5%

Reference Manual     : IMX6DQPRM Rev. 1, 09/2017  : 100 51.5% low 48.5% high

Reference Manual     : IMX6DQPRM Rev. 2, 06/2018  : 100 Reserved

I afraid to make mistake because my customer will be start their production based on this update.

Best regards,

Ishii.

0 件の賞賛
返信
1,416件の閲覧回数
takayuki_ishii
Contributor IV

Hello community,

In EB817(SDCLK Duty Cycle Optimizations for i.MX 6Quad/6Dual), it say that CK_FTx_DCC=100 is reserved.

Does it have some difference between i.MX6 DualPlus/QuadPlus and Dual/Quad?

Or is it a mistake in document EB827?

Best regards,

Ishii.

0 件の賞賛
返信
1,416件の閲覧回数
takayuki_ishii
Contributor IV

Hello community, 

Some one help me?

I hope know a correct specification and recommended register value of i.MX6QuadPlus.

Best regards,

Ishii.

0 件の賞賛
返信