Are MIPI CSI2 "line start" & "line end" Mandatory ?

[stephanetavenar]

Hi,

We are using iMX6Q and DS90UB954 Ti Deserialiser for capturing video from 2 cameras.

The DS90UB954 is connected to MIPI-CSI2 interface of iMX6Q, using 2 lanes.

The status (PHY_STATE) register show that clock is present (0x00000300), but register MIPI_CSI_ERR1 vlaue is often  0x01001000 (CRC errors)

MIPI_CSI2 signals haved been checked with MPI-CSI2 analyzer (frames ok and no CRC error found)

However, DS90UB954 don't generate short packet frames "line start" and "line end", only short packets "frame start" a "frame end" are present. Do you know if this short packets "line start" and "line end"  are mandatory for IMX6Q MIPI-CSI2 interface ?

Thanks.

[stephanetavenar]

Hi Igor,

You are right. It's confirmed, these short packets are not mandatory.

My problem was in fact a wrong Datatype settings by the v4l2driver into the IPU CSI register CSI_MIPI_DI.

The linux mainline version of this driver does not support my frame datatype, RGB888 (DT=0x24).

In this case a wrong DT  of 0x1 was set by mistake, so the frames were filtered.

Problem solved.

Thanks.

Stephane

[zhengl]

I am using a Deserializer TI DS90UB940 in RGB888 with iMX6, but in the data get from channel the pixel data 's RGB value order is random, a all red data looks like  FF000000FF000000FFFF000000FF000000FFFF000000FF000000FFFF000000FF

, It is supposed to be something like FF0000FF0000FF0000FF0000FF0000, 

If you met any problem like this?

[stephanetavenar]

Thanks igor for your response. But I'm taking about MIPI-CSI2 "short" packets (DT=0x02 & DT=0x03), is there any link with hsync signal ?

Regards,

Stephane

[igorpadykov]

Hi Stephane

if it is about MIPI-CSI2 specification, seems it is optional as described on p.21 presentation

http://rfmw.em.keysight.com/mod/pdf/axie_u4421a_mipi_d-phy_protocol_fundamentals_detailed_presentati... 

Best regards
igor

[igorpadykov]

Hi Stephane

seems it is not mandatory as explained on p.15 appnote:

MIPI CSI2 data transferred from MIPI CSI to IPU Gasket to IPU CSI,

it is always in non-gated clock mode..(hsync signal is not used)

iMX6 IPU TVIN Application Notes 

also may be useful to check

iMX6DQ MAX9286 MIPI CSI2 720P camera surround view solution for Linux BSP 

Best regards
igor
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