About i.MX6 Internal LDO

[okamotosatoshi]

Hello.

I want to check about i.MX6Q.

Thank you to answer the following questions.

We have created a custom board of i.MX6Q.

I confirmed the voltage drop in VDDSOC_CAP at startup.

I attach the measured waveform. (VDDSOC_CAP : No load)

CH1：5V(Power-supply voltage)

CH2：2.5V(VDDHIGH_CAP)

CH3：1.1V(VDDSOC_CAP)

CH4：POR_B

Is there a way to avoid the voltage drop of VDDSOC_CAP ?

In addition, the voltage drop of VDDSOC_CAP was Would no issue ?

Start-up failure has occurred on the SATA boot.

Believes that the above reason.

(For reset release timing occurred voltage drop of VDDSOC_CAP.)

Regards,

-satoshi

[okamotosatoshi]

Hi, chip

Thank you for reply.

I was relieved at the fact that no problem waveform.

It was confirmed to I get information, but would not be applicable items.

I confirmed the similar symptoms in other substrates.

- incorrect capacitor value on VDDSOC_CAP

A)VDDSOC_CAP have placed more than capacitor of 22uF.

　No change If you place a 100uF.

- incorrect current capability on VDDSOC_IN from PMIC

- incorrect power-up sequence

A)There is no problem because you have the power generated by the PMIC.

　(As with SABRE Board.)

If you 100uF capacitor , the voltage at the first time is reduced.

Thereafter , it is a normal voltage rise for the second time.

(Discharge curve becomes gentle.)

From the above , I believe the rise of the first time that he crowded around the power of other i.MX6.

After that , it seems to be a constant load discharge.(Measured values with the calculated values match almost.)

I believe the rise of the second is correct output voltage of the LDO.

I think the issue i.MX6 series.

Are there any plans to improve this problem ?

This phenomenon will not occur in SABRE Board?

CPU：MCIMX6Q5EYM10AC

PMIC：MMPF0100F0AEP

Regards,

-satoshi

[okamotosatoshi]

Hi, chip

I will append the contents measured .

Please refer to the attached document for details.

・VDDSOC_CAP/VDDPU_CAP wraps around VDDHIGH_IN is supplied.

・When VDDHIGH_IN turn off, LDO is not outputted.

　(VDDHIGH_IN enabled internal LDO?)

・Rising edge of the second time changes.(VDDSOC_CAP/VDDPU_CAP)

　(You are shifting inside the output timing ?)

・Rising edge of the first have the same timing.(VDDSOC_CAP/VDDPU_CAP)

From the above, I believe that wraps around from VDDHIGH_IN.

①VP power supply is no issue using VDDSOC_CAP?

②Are there any plans to improve this issue ?

③This phenomenon will not occur in SABRE Board?

Regards,

-satoshi

[igorpadykov · Accepted solution]

Hi okamoto

in general there is nothing wrong in these

waveforms. Transients and glitches are allowed,

during this time POR should be asserted.

①VP power supply is no issue using VDDSOC_CAP?

No issue.

②Are there any plans to improve this issue ?

No plans, because it is allowed.

③This phenomenon will not occur in SABRE Board?

SABRE Board may have incorrect waveforms because it was designed

in time when i.MX6 datasheets were not finalized.

Best regards

chip

[okamotosatoshi]

Hi, chip

Thank you for reply.

I will assert POR during the waveform.

Thank you for information.

Asserting the POR until normal operation.

Then use it to reset release.

Best regards

-satoshi

[igorpadykov]

Hi okamoto

in general there is nothing wrong in these

waveforms.

VDDSOC_CAP sag may be caused by several reasons:

- incorrect power-up sequence

- incorrect capacitor value on VDDSOC_CAP

- incorrect current capability on VDDSOC_IN from PMIC

Please check all above with Chapter 2 Design Checklist,

Chapter 4 Requirements for Power Management,

Chapter 8 Avoiding Board Bring-up Problems

IMX6DQ6SDLHDG IMX6DQ6SDLHDG, Hardware Development Guide

Best regards

chip

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