About SDR50/SDR104 Interface Timing Specification in i.MX6DQ.

[keitanagashima]

Dear All,

Refer to Table 56. SDR50/SDR104 Interface Timing Specification in IMX6DQAEC_Rev.3.

It was described "SD5 uSDHC Output Delay".

Next, refer to Figure 47. SDR50/SDR104 Timing.

I think that "SD4" is correct allow because parameter name is "uSDHC Output Delay".

Please check it.

Best Regards,

Keita

[Yuri · Accepted solution]

Yes, I think we have some inaccuracy here.

SD4 is output delay of data assertion from uSDHC (to card).

SD5 is output delay of data assertion from card (to uSDHC).

I will inform the doc team about it.

Have a great day,
Yuri

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