About IMX8MQ chip using MIPI CSI-2 to receive IM390 camera data stream

[Gonglja]

Hi,

       developers of nxp,I am using the IMX8MQ platform to access the IMX390 camera to directly output the video data stream, and now I cannot receive the data stream on the IMX8 side.

       I have set up the device tree with reference to this  configuration , and now I can see the /dev/video* node, please provide me with some help, ths.

[Gonglja]

Can you provide detailed documentation for imx8mq configuration csi2 clock interface configuration？

[joanxie]

as I known, IMX390 should output raw data, right? if yes, imx8mq couldn't handle raw data directly

[Gonglja]

joanxie,thank you for your reply .

      I don’t know the specific parameters, but I can already capture 1920x1080@30 uyuv data stream through gst-launch1.0.

      The camera solution uses imx390 -- serialization chip -- coaxial cable -- deserialization  chip -- imx8mq,but I have another problem. The mipicsi2 data output by the serialization chip is 1600Mbps. I use 4lane to receive it. I can use gst-lanuch1.0 to display the captured video through HDMI, but the video will continue to pan in the horizontal direction. Like the animated picture, can you give me some help, thank you very much

[joanxie]

OK, I thought you add the imx390 directly, did you change the clock in the dts file? if the output is 1600Mbps, it seems that 2-lane can support it already

[Gonglja · Accepted solution]

Yes, the camera output is currently using 4 lanes, each lane is 400Mbps, I modified the clock under .dtsi, as follows:

	csi1_bridge: csi1_bridge@30a90000 {
		compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi";
		reg = <0x0 0x30a90000 0x0 0x10000>;
		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_DUMMY>,
			<&clk IMX8MQ_CLK_CSI1_ROOT>,
			<&clk IMX8MQ_CLK_DUMMY>;
		clock-names = "disp-axi", "csi_mclk", "disp_dcic";
		status = "disabled";
	};	
mipi_csi_1: mipi_csi1@30a70000 {
		compatible = "fsl,mxc-mipi-csi2_yav";
		reg = <0x0 0x30a70000 0x0 0x1000>; /* MIPI CSI1 Controller base addr */
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk IMX8MQ_CLK_DUMMY>,
				<&clk IMX8MQ_CLK_CSI1_CORE>,
				<&clk IMX8MQ_CLK_CSI1_ESC>,
				<&clk IMX8MQ_CLK_CSI1_PHY_REF>;
		clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
		assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
				  <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
				  <&clk IMX8MQ_CLK_CSI1_ESC>;
		assigned-clock-rates = <266000000>, <125000000>, <133000000>;
		power-domains = <&mipi_csi1_pd>;
		csis-phy-reset = <&src 0x4c 7>;
		phy-gpr = <&gpr 0x88>;
		status = "disabled";
	};

I modified assigned-clock-rates.

assigned-clock-rates = <266000000>, <125000000>, <133000000>;

[joanxie]

how about changing to assigned-clock-rates = <266000000>, <333000000>, <66000000>?

[Gonglja]

Thank you for your reply. The image problem is actually the configuration problem of video on another chip, which leads to the image translation of our chip after bypass.

[Gonglja]

I can't get the image information directly by using the above configuration.

[Gonglja]

I'll try, but I know from imx8mdqlqrm.pdf that maximum Mipi_ CSI1_ PHY_ REF_ CLK_ROOT is 125MHz, Mipi_ CSI1_ ESC_ CLK_ROOT is 133 MHz.