About Boot Configuration of i.MX6

[okamotosatoshi]

Hello.

I want to check about i.MX6Q.

Thank you to answer the following questions.

①BOOT_CFG1[4]　("Override Pad Settings")

Do you match in recognition of the following ?

Set "0"　-　To use the settings of the config terminal.(GPIO)

Set "1"　-　To use the settings of PAD_SETTINGS register.

②BOOT_CFG1[4]　("Override Pad Settings")

The use of the setting PAD_SETTINGS register , do you when you select the "toggle mode NAND" in BT_TOGGLEMODE?

③BOOT_CFG2[7：5]　("Toggle Mode -　Latency")

What should be selected if you have selected the "raw NAND" in "BT_TOGGLEMODE"?

④BOOT_CFG2[4：3]　("Boot Search Count")

Please tell me how to use it.

What do a setting to do what for the condition?

⑤Fusemap

There is a difference by BOOT_CFG1 [1:0] in P359 "Table 5-9.NAND Boot Fusemap" and P411 "Table 8-11.NAND Boot eFUSE Descriptions".

Which is correct ?

Regards,

-okamoto

[qiang_li-mpu_se]

①BOOT_CFG1[4]　("Override Pad Settings")

Do you match in recognition of the following ?

Set "0"　-　To use the settings of the config terminal.(GPIO)

Set "1"　-　To use the settings of PAD_SETTINGS register.

[Qiang] when this is 0, the boot rom will use default setting for NAND related pins in registers IOMUXC_SW_PAD_CTL_PAD_NAND_xxx will be set to their default value as iMX6 reference manual described. When this is 1, these IOMUXC_SW_PAD_CTL_PAD_NAND_xxx registers will be set to PAD_SETTINGS values in fuse.

②BOOT_CFG1[4]　("Override Pad Settings")

The use of the setting PAD_SETTINGS register , do you when you select the "toggle mode NAND" in BT_TOGGLEMODE?

[Qiang] "Override Pad Settings" has no business with "toggle mode NAND".

③BOOT_CFG2[7：5]　("Toggle Mode -　Latency")

What should be selected if you have selected the "raw NAND" in "BT_TOGGLEMODE"?

[Qiang] "Toggle Mode -　Latency" only apply to toggle mode NAND. The delay value should be checked from the customer NAND's datasheet.

④BOOT_CFG2[4：3]　("Boot Search Count")

Please tell me how to use it.

What do a setting to do what for the condition?

[Qiang] How many FCB copies in NAND can be searched by boot ROM, based on Freescale default BSP, it is 4. To define 8 Search Count, the board will be more strong to avoid boot failure, of cource, you also need programe 8 FCBs into the NAND.

⑤Fusemap

There is a difference by BOOT_CFG1 [1:0] in P359 "Table 5-9.NAND Boot Fusemap" and P411 "Table 8-11.NAND Boot eFUSE Descriptions".

Which is correct ?

[Qiang] After checked the boot ROM source code, P411 is correct, 00 - 3; 01 - 2; 10 - 4; 11 - 5. It is a document issue.

[okamotosatoshi]

Hi, Qiang

Thank you for reply.

①：Was understood to choose PAD_SETTINGS setting of the fuse or settings register.

②：Was understood that there is no relation to the setting of BT_TOGGLEMODE.

③：was understood to set the delay value when selected the "toggle mode NAND".

　　If you select the "raw NAND", What should I set ?

④：I was able to understand a little .

⑤：was  understood the contents of the P411 is correct.

Regards,

-okamoto

[qiang_li-mpu_se]

For the "Boot Search Count", it depends on the programed NAND layout.

For example, based on Freescale default BSP, this value is 4. Then on the NAND flash, block 0 ~ 3 will be used to store four copy of FCB, and the Freescale board will set "Boot Search Count" to 4 too, then when iMX6 boot up, the boot ROM will search FCB from block 0 ~ 3 for boot up. If the boot ROM found a valid FCB, it will continue to boot the board. In this case, when time goes on, even though block 0, 1, 2 became bad block, the board still can boot up due to there is still a valid FCB in block 3.

And if you want to set "Boot Search Count" to 8, then you need programe 8 copy of FCB to NAND block 0 ~ 7.

[okamotosatoshi]

Hi, Qiang

Thank you for reply.

There is a question of "Override Pad Settings" of BOOT_CFG1 [4].

If set to "1", "Use PAD_SETTINGS value" is selected .

At this time, I think that "PAD_SETTINGS [5:0]" of "Address:0x6d0" is reflected.

To set the PAD_SETTINGS to blow fuses?

Also, setting value reflects a common setting (Slew Rate/Drive Strength/Speed Settings) for each IOMUXC_SW_PAD_CTL_PAD_NAND_xxx?

Regards,

-okamoto

[qiang_li-mpu_se]

The PAD_SETTINGS fuse is a common setting for all IOMUXC_SW_PAD_CTL_PAD_NAND_xxx pins.

[okamotosatoshi]

Hi, Qiang

Thank you for reply.

Advice was very helpful.

Reply also fast and I thank sincerely.

Regards,

[qiang_li-mpu_se]

For ③, when "raw NAND" was used, the delay value can be set to default value 000, they are not used.

[okamotosatoshi]

Hi, Qiang

Thank you for reply.

Advice was very helpful.

Reply also fast and I thank sincerely.

Regards,

-okamoto