APBH DMA and GPMI Interrupts

[jaysherritt]

Hi,

I'm writing a device driver for NAND Flash for the i.MX 6 (DQ), and would like to have it be fully interrupt driven.  The documentation for the APBH_DMA in the reference manual (14.5.2) states "Each channel has a dedicated interrupt vector in the vectored interrupt controller.", however, I'm unable to find these in the interrupt map, and my read of the Linux driver is that it only uses interrupts to indicate the end of transfers where the BCH encoding is enabled.

The CHxCMDCMPLT_IRQ bit(s) in the APBH_CTRL1n register are being set appropriately in accordance with my channel commands (and enabled by the CHxCMDCMPLT_IRQ_EN bits), but I haven't found any way to promulgate these back to the GIC.

How do I get an interrupt at the end of a descriptor phase when BCH encoding or decoding is not enabled?

Thanks.

Jay

[Yuri]

Hello,

  Please refer to Table 3-1 (ARM domain interrupt summary),

where IRQ 45 as “APBH-Bridge-DMA Logical OR of APBH-Bridge-DMA

channels 0-3 completion and error interrupts” is shown.

  It is needed to check interrupt request status bits in APBH_CTRL1n to define

source of the event in ISR. 

Have a great day,
Yuri

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