Hard Fault on SEMA4 CP1INE access?

[eruanno]

Hello,

I would like to run a simple application that uses hardware semaphores on phyCore board (Vybrid PVF65GS10CMK40 test rev.). I have a problem with

modifying CP1INE register. Whatever I do, any write access to this register causes Hard Fault.

This is a code sample:

#define GATE (*(volatile unsigned char*)(0x4001D000))

#define CPINE (*(volatile unsigned short*)(0x4001D048))

int main()

{

     SystemInit();          // Sets vector table and  enables all peripheral clocks excepting GPU

     CPINE = 0x1000;

     GATE = 2;

     while(1)

     {

     }

}

[simonkunzmann · Accepted solution]

Hi Matthew,

I had the same problem and this was the solution:

The Reference Manual states that the offset to the SEMA4_CP1INE Register is 48, but when i take a look at the SEMA4_MemMap struct  in the "MVF50GS10MK50.h" file the offset seems to be  50:

/** SEMA4 - Peripheral register structure */  
typedef struct SEMA4_MemMap {  
  uint8_t GATE[16];  
  uint8_t RESERVED_0[50]; /* 48 */  
  uint16_t CP0INE;                                 /**< Semaphores Processor n IRQ Notification Enable, offset: 0x40 */  
  uint8_t RESERVED_1[6];  
  uint16_t CP1INE;                                 /**< Semaphores Processor n IRQ Notification Enable, offset: 0x48 */  
  uint8_t RESERVED_2[54];  
  uint16_t CP0NTF;                                 /**< Semaphores Processor n IRQ Notification, offset: 0x80 */  
  uint8_t RESERVED_3[6];  
  uint16_t CP1NTF;                                 /**< Semaphores Processor n IRQ Notification, offset: 0x88 */  
  uint8_t RESERVED_4[118];  
  uint16_t RSTGT;                                  /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */  
  uint8_t RESERVED_5[2];  
  uint16_t RSTNTF;                                 /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */  
} volatile *SEMA4_MemMapPtr;  

maybe this helps.

Best Regards

Simon

[eruanno]

Hi Simon,

It seems to work now! Thanks for help.

Best regards

Matthew

[eruanno]

I am sorry, out of habit, I have pressed Ctrl+S and that caused sending my question :smileyhappy: before I finished writing it. More details here:

This is an excerpt from disassembly. As you can see I use 16-bit access to write CP1INE. Read access does not cause Hard Fault.

0x3F00037C : LDR      r0,[pc,#32] ; [0x3F0003A0] = 0x4001D000

0x3F00037E : MOV      r1,#0x1000

0x3F000382 : STRH     r1,[r0,#0x48]

0x3F000386 : MOVS     r1,#2

0x3F000388 : STRB     r1,[r0,#0]

Besides on HardFault CFSR is set to 0x00000400 (IMPRECISERR).

Did I miss something? May it be a silicon bug (eventually this is test PF revision)?

Thanks in advance.

[alejandrolozan1]

Hi Matthew,

I have seen that the most common reason that generates a hard fault is trying to write to a module whose clock gate is off.

Make sure that the correct CCM_CCPGRn bits and register is set for the SEMA4 module.

I hope that helps,

Alejandro

[eruanno]

Hi Alejandro,

Thanks for reply. I was able to lock the gates by writing the core number + 1 to GATE registers so SEMA4 module clock was on. I have not modified CCPGR bits as they are set after reset by default.

The Simon's hint was good direction to solve the problem.

Best regards,

Matthew