T1040 cfg_rcw_src[6:7] Confusion

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T1040 cfg_rcw_src[6:7] Confusion

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nsutch
Contributor III

There appears to be a conflict in the T1040 Reference Manual (rev, 1 08/2015) regarding the options for cfg_rcw_src[6:7] between page 198 and page 1011. While a shift of 4 or 7 bits correlate between the two sections (bit [6:7] = 10 or 01, respectively), the remaining settings do not match...

Page 1011
if cfg_rcw_src[6:7]=00 (00 22b addressability) then ADM_SHFT = 10
if cfg_rcw_src[6:7]=01 (00 25b addressability) then ADM_SHFT = 7
if cfg_rcw_src[6:7]=10 (00 28b addressability) then ADM_SHFT = 4

Page 198/199
cfg_rcw_src[6:7]:
00 Reserved
01 Shift left by 7 to provide up to 25b addressability OR shift right by appropriate amount (depends on Port Size selected) and provide up to 25b addressability.
10 Shift left by 4 to provide up to 28b addressability OR shift right by appropriate amount (depends on Port Size selected) and provide up to 28b addressability.
11 Shift left by 0 to provide up to 32b addressability OR shift right by appropriate amount (depends on Port Size selected) and provide up to 32b addressability.

Ultimately, I am intending to use NOR flash with a left shift of 0. Other than highlighting an error in the RM, is setting cfg_rcw_src[6:7] = 11 a valid combination?

Thanks,

Nick

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ufedor
NXP Employee
NXP Employee

The cfg_rcw_src[6:7] = 11 is a valid setting for the 32-bit NOR Flash.

The setting:

   Page 1011
   if cfg_rcw_src[6:7]=00 (00 22b addressability) then ADM_SHFT = 10

is a typo because T1040 does not support 22-bit IFC address.

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ufedor
NXP Employee
NXP Employee

The cfg_rcw_src[6:7] = 11 is a valid setting for the 32-bit NOR Flash.

The setting:

   Page 1011
   if cfg_rcw_src[6:7]=00 (00 22b addressability) then ADM_SHFT = 10

is a typo because T1040 does not support 22-bit IFC address.

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