How to set T2080 HWA_CGA_M2_CLK_SEL RCW value

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How to set T2080 HWA_CGA_M2_CLK_SEL RCW value

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gregbuchannan
Contributor I

The T2080 QorIQ RM describes HWA_CGA_M2_CLK_SEL as controlling "Cluster group A, mux 2 clock select
used for eSDHC SDR mode" , but there is no indication of what the selected clock ratio actually controls.  How does one determine the correct value for this configuration field?

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r8070z
NXP Employee
NXP Employee


Have a great day,

RCW[HWA_CGA_M2_CLK_SEL] bits select clock source (Cluster group A PLL2, Cluster group A PLL1, Cluster clock) and division factor for the source clock (1:1, 1:2, 1:3, 1:4) used by eSDHC module. HWA_CGA_M2_CLK_SEL values for possible sets of the clock sources and division factors you can see in Table 4-14. RCW Field Descriptions (Bits 509-511) of the T2080 reference manual rev.3. Please see also Figure 4-3. T2080 Logic Clock Subsystem Block Diagram in the manual.

Clock selected by HWA_CGA_M2_CLK_SEL is mentioned in the manual chapter 16 Enhanced Secured Digital Host Controller (eSDHC) as “peripheral clock”. It can be divided with finer granularity in order to produce the SD clock. In this case one selects HWA_CGA_M2_CLK_SEL value suitable for required SD clock frequencies. Otherwise it does not care.

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gregbuchannan
Contributor I

Serguei,

Thanks so much for your helpful reply.   Could you clarify what is meant by " eSDHC SDR mode" in the RM?  I was assuming this RCW setting was related to a synchronous SD mode only?

Regards,

Greg 

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