Reset Configuration World(RCW) PLL ratio not affecting SYSCLK Frequency Value

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Reset Configuration World(RCW) PLL ratio not affecting SYSCLK Frequency Value

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vinothkumars
Senior Contributor III

Hi All,

I am confused about the SYSCLK_FREQ rcw value on the T4160RDB and I referred the T4240RM.pdf for RCW filed discription.

Here is the hard-coded RCW value for T4160RDB:


Reset Configuration Word (RCW):
Data.Set DBG:0x01000000 0x1406000F
Data.Set DBG:0x01000001 0x0A080808
Data.Set DBG:0x01000002 0x00000000
Data.Set DBG:0x01000003 0x00000000
Data.Set DBG:0x01000004 0x6C6E2848
Data.Set DBG:0x01000005 0x30548c00
Data.Set DBG:0x01000006 0xFC02F000
Data.Set DBG:0x01000007 0x1D000000
Data.Set DBG:0x01000008 0x00000000
Data.Set DBG:0x01000009 0xEE0000EE
Data.Set DBG:0x0100000A 0x00000000
Data.Set DBG:0x0100000B 0x000307FC
Data.Set DBG:0x0100000C 0x00000000
Data.Set DBG:0x0100000D 0x00000000
Data.Set DBG:0x0100000E 0x00000000
Data.Set DBG:0x0100000F 0x00000008

the RCW value we are using is  Data.Set DBG:0x01000000  0x1406000F
1406000F -> 1406 -> 0001 0100 0000 0110
2-6 is 0_1010 ie system PLLratio is 10:1. platform clock is 10X SYS_CLK = 666.66MHZ
10-15 is 00_0110 is DDR PLL ratio is 12:1. DDR rate is 12X DDR clock = 12 x 133.33 = 1600

;Calculation of UART settings for 115200Bd

;Get PLL ratio from RCW for correct DUART settings
&SYS_PLL_RAT="((data.long(ANC:iobase.address()+0xE0100)>>25.)&0x0000001F)" 

Please give some detailed explanation for find uart baud rate by rcw pll ratio.

What could be the issue?

Thanks, VinothS

Regards,
Vinothkumar Sekar
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ufedor
NXP TechSupport
NXP TechSupport

Each UART contains an independent programmable baud-rate generator, that is capable of taking the [platform clock frequency]/2 as input and dividing the input by any divisor from 1 to 2^16 - 1.


The baud rate is defined as the number of bits per second that can be sent over the UART bus. The formula for calculating baud rate is as follows:


Baud rate = (1/16) x (([platform clock frequency]/2) ÷ divisor value)


Therefore, the output frequency of the baud-rate generator is 16 times the baud rate.


The divisor value is determined by the following two 8-bit registers to form a 16-bit binary number:

• UART divisor most significant byte register (UDMB)
• UART divisor least significant byte register (UDLB)
Upon loading either of the divisor latches, a 16-bit baud-rate counter is loaded.

For implementation in U-Boot refer to the  u-boot/board/freescale/t4rdb/spl.c function "board_init_f"

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ufedor
NXP TechSupport
NXP TechSupport

Each UART contains an independent programmable baud-rate generator, that is capable of taking the [platform clock frequency]/2 as input and dividing the input by any divisor from 1 to 2^16 - 1.


The baud rate is defined as the number of bits per second that can be sent over the UART bus. The formula for calculating baud rate is as follows:


Baud rate = (1/16) x (([platform clock frequency]/2) ÷ divisor value)


Therefore, the output frequency of the baud-rate generator is 16 times the baud rate.


The divisor value is determined by the following two 8-bit registers to form a 16-bit binary number:

• UART divisor most significant byte register (UDMB)
• UART divisor least significant byte register (UDLB)
Upon loading either of the divisor latches, a 16-bit baud-rate counter is loaded.

For implementation in U-Boot refer to the  u-boot/board/freescale/t4rdb/spl.c function "board_init_f"

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vinothkumars
Senior Contributor III

Hi Ufedor,

UDLB = 0x48

UDMB = 0

Accorrding PLL Ratio ( 6:1)

processor clock = 666.66MHZ

How will calculate Divisor Value from UDLB and UDMB ?

 

Thanks & Regards,

VinothS

Regards,
Vinothkumar Sekar
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vinothkumars
Senior Contributor III

Hi Ufedor,

Thank you for quick response.

Thanks & Regards,

VinothS

Regards,
Vinothkumar Sekar
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