I am having a customised board with T1022 processor, we are having xilinx FPGA and is connected via IFC bus CS3.
Currently it is connected on IFC bus with CS3 , on doing respective settings of the chip select option register, property register and timing register in the uboot the same is reflected in uboot[by reading the cpu register] but on manually probing the Chip Select using CRO/scope no transition is visible on CS3.
Currently value of the three FLASH timing register is 0xE00E00E, 0x0E001F00, 0x0E20001F.
We are also having CPLD on CS2 and are able to access CPLD .
Setting only 0xE00E00E, 0x0E001F00, 0x0E20001F values is not enough. Looking to these values, I can guess you are using these values for FTIM1, FTIM2 and FTIM3 registers. Setting only these registers is not enough, you have to also set at least CSPRn, CSPRn_EXT and AMASKn (where n is your CS number).
Please look T1040 Reference Manual, Section 24.3 for more details.
In addition to proper setting of IFC-related registers, please also do not forget to configure Local Access Window (LAWn) by proper setting registers LAW_LAWBARHn, LAW_LAWBARLn and LAW_LAWARn
See Section 2.4 for more details.
T1040 Reference Manual is available for download from T1040 Product Page, "Documentation" tab:
Have a great day,
Alexander
TIC
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We have set the option register , property register and mask register , the same were correctly read from uboot.
The current configuration of CPU register read from u-boot is as follows -
For LAW-
LAWn base address register high (LAW_LAWBARH2) = 0000000f
LAWn base address register low (LAW_LAWBARL2) = ffdf0000
LAWn attribute register (LAW_LAWAR2) = 81f00010
For CSPRn, CSPRn_EXT and AMASKn , timing registers -
Extended Chip Select Property registers (IFC_CSPR3_EXT) = 0000000f
Chip-select Property register n (IFC_CSPR3) = ffdf0105
Address Mask register (IFC_AMASK3) = ffff0000