Activating cores 1-3 in T1042 (U-Boot + bare-metal)

[ricardofranca]

Hello,

I am playing with a T1042 in an Embedded Planet EPT1042xS development board and, while I am able to use the U-Boot load and "go" command to run bare-metal applications on Core 0, I do not know how to make use of the other cores. It seems U-Boot enables them (DCFG_CCSR_COREDISR = 0x0 and DCFG_CCSR_BRR = 0xf) but it seems not to do anything when I use the core release commands, e.g. "core 1 release 0x24000 - - -" to make a core run some function (even if the function did not use stack and simply had to write in a known memory address).

Where should I start in order to do get other cores to work?

Thanks!

[Bio_TICFSL]

Hello,

Only the bootcore will be executing u-boot code. Under some circumstances, the PPA will release 1 or 2 secondary cores for its own use during boot. In regards to Linux, Linux calls into the ppa to release secondary cores one-by-one. Linux uses the standard PSCI interface to release the cores. They are initialized by the ppa and then delivered to the kernel. This has been working well for years on the LS2088 ans T1042. U-boot plays no part in releasing the secondary cores. The cores are released as the kernel requests them. The kernel asks for each core specifically by core number (mpidr) and the ppa releases just that core to the kernel. If the kernel requests one of the cores that ppa is holding in wfe, then that core is released from wfe and delivered to the kernel. If the kernel requests a core, and that core is NOT delivered in a reasonable time, then the kernel throws an error. Summarizing, at Uboot prompt, core 0, 1, 2 are released (with 1 and 2 in WFE state) while core 3~7 are not. In Linux, all 8 cores are released by PPA, requested by kernel. The quickest way to check if the cores are released in LInux is to do "cat /proc/cpuinfo

Regards