S32K11x - SM_119

[Catosh]

Hi all, 

about [SM_119]:" The Flash memory ECC failure reporting path should be checked to validate if detected ECC faults are correctly reported. [end]"

The implementation hint :"The flash memory ECC fault report check is executed in software".

I would like to understand what does the implementation hint mean. 

In my application I enable the double bit fault detect interrupt and then I force an ECC error:

FTFx_FERCNFG |= FTFx_FERCNFG_DFDIE_MASK;

FTFx_FERCNFG |= FTFx_FERCNFG_FDFD(1);

uint32_t tempvar = (uint32_t)*((uint32_t*)(0x4));// Reset vector address here

This triggers the ecc controller and generates the expected interrupt. In the FTFC_IRQHandler, i relocate the callback (so no more ECCs are generated) for checking if the ECC was a real error or a test.

In case of error if no FTFx_FERCNFG_FDFD(1) was present in FTFx_FERCNFG i enter in a safe state. 

is this considered a ECC fault report check or am I out of track?

K.R.

Luca.

[atzelcollazo · Accepted solution]

Hello Catosh,

Yes, that is consider an ECC check. The implementation hint means the application is the one in charge to perform the flash memory ECC check. As long as you check the ECC mechanism is working as expected, the [SM_119] is covered.

NOTE:

The current version of the RM is not mentioning the real behavior of the SoC when a double bit error occurs. This behavior will be added in the next rev of the RM [Rev12]. In the case of a double bit error the Flash module will report the error to the crossbar which will trigger a BusFault error. If the BusFault error is not enabled [The default state is disabled] the HardFault error will be triggerd. After serving the BusFault or the HardFault interrupt in case the BusFault is not enabled, the ECC double bit error interrupt will be serviced.

Best Regards,

Atzel Collazo

[Catosh]

Hi Alejandro, 

thanks for your reply. 

About your note: according to ARM v6 architecture:

and

My question here: how can I test the SRAM ECC interrupt on the CM0+ mcus if the interrupt is mapped to the hard fault? It's obvious that triggering a sw reset each FTTI is not feasible. Is it safe to exit from the Hard Fault Handler in this scenario?

(Similar issue for MPU or unimplemented space: the error escalates to Hard fault handler since there is no bus fault handler on CM0+.)

Any hint would be gladly appreciated.

K.R.

Luca

[atzelcollazo]

Hello Catosh,

The interrupt is not mapped to the HardFault, it is generated becasue the Flash module reports an error to the crossbar. I forgot so specify that note is only applicable for Flash errors not for errors in RAM.

Best Regards,

Atzel Collazo