How to verify the clock(SPLL/SOSC) via injecting the fault so we can observe the reset

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How to verify the clock(SPLL/SOSC) via injecting the fault so we can observe the reset

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507 次查看
vishnukumar_n
Contributor II

Hi,

I am working on functional safety application for clock monitoring for S32K146 and I have 2 query

1. I have configured the SPLL and SOSC. As per my application, I am resetting the device incase SPLL and SOSC loss the clock happens.
SCG_SOSCCSR[SOSCCM] - System OSC Clock Monitor: I have enabled it
SCG_SOSCCSR[SOSCCMRE] - System OSC Clock Monitor Reset Enable : I have enabled it

SCG_SPLLCSR[SPLLCM] - System PLL Clock Monitor : I have enabled it
SCG_SPLLCSR[SPLLCMRE] - System PLL Clock Monitor Reset : I have enabled it


RCM_SRIE[LOL] - Loss of Lock Interrupt: I have enabled it

RCM_SRIE[LOC] - Loss of Clock Interrupt: I have enabled it

now how to inject the fault in clock (SOSC/SPLL) so that I can verify reset due to missing the clock?

2. as per the safety manual S32K1XXSM_Rev5.pdf section SM_213 Implementation hint, it is described that we can verify PLL output.

now my thinking is, if we are using below setting in EBTresos for clock configuration

SCG_SOSCCSR[SOSCCM] - System OSC Clock Monitor: I have enabled it
SCG_SOSCCSR[SOSCCMRE] - System OSC Clock Monitor Reset Enable : I have enabled it

SCG_SPLLCSR[SPLLCM] - System PLL Clock Monitor : I have enabled it
SCG_SPLLCSR[SPLLCMRE] - System PLL Clock Monitor Reset : I have enabled it


RCM_SRIE[LOL] - Loss of Lock Interrupt: I have enabled it

RCM_SRIE[LOC] - Loss of Clock Interrupt: I have enabled it

then additionally SM_213 implementation hint is not required. is my understanding correct ?

looking your feedback soon...

Thanks

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462 次查看
aarul
NXP Employee
NXP Employee

Hi

1. For fault injection, you can try to change the PLL settings or inject the fault through hardware (eg: disconnect the crystal) to verify that reset is triggered.

2. The assumption is required to safeguard against multiple point faults. It gives additional confidence that the clocks are correctly configured and the lock circuit is not indicating a false lock.

Hope this helps,

Regards

-Aarul

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463 次查看
aarul
NXP Employee
NXP Employee

Hi

1. For fault injection, you can try to change the PLL settings or inject the fault through hardware (eg: disconnect the crystal) to verify that reset is triggered.

2. The assumption is required to safeguard against multiple point faults. It gives additional confidence that the clocks are correctly configured and the lock circuit is not indicating a false lock.

Hope this helps,

Regards

-Aarul

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476 次查看
vishnukumar_n
Contributor II

any update on this?

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