I thought this problem was fixed, but it has come back.
We are using the s32k146 processor.
When I erase and write new data to the data flash memory, after the write, when reading from address 0x10000000, I get the old data and not the newly written data. Power cycling will fix this, but we don't want to have this limitation.
I asked this question before and got a response which led me to the OCM1 field of the OCMDR[1] register. I used this to disable and renable the cache, and tested and got good results. But I guess I was just lucky, because now I am back to having this problem.
Below is the code where we write to the flash memory, beginning and ending with the code to disable/enable the cache. Is something missing?
MSCM->OCMDR[1] |= MSCM_OCMDR_OCM1(1); //disable data flash cache
EraseFlash(0); //erases the whole "block" however much that is, but more than just 8 bytes
FTFC_FCCOB0 = 0x7; //Program phrase
FTFC_FCCOB1 = 0x80;
FTFC_FCCOB2 = 0;
FTFC_FCCOB3 = 0;
FTFC_Data0 = ((int*) &incomingConfigs)[0];
FTFC_Data1 = ((int*) &incomingConfigs)[1];
FTFC->FSTAT |= FTFC_FSTAT_CCIF_MASK; //clear CCIF by writing 1 to it
while ((FTFC->FSTAT & FTFC_FSTAT_CCIF_MASK) == 0)
{}
FTFC_FCCOB3 = 8;
FTFC_Data0 = ((int*) &incomingConfigs)[2];
FTFC_Data1 = 0xFFFFFFFF;
FTFC->FSTAT |= FTFC_FSTAT_CCIF_MASK; //clear CCIF by writing 1 to it
while ((FTFC->FSTAT & FTFC_FSTAT_CCIF_MASK) == 0)
{}
MSCM->OCMDR[1] &= MSCM_OCMDR_OCM1(2); //enable data flash cache
