Hello Team
Need help in controlling Flexio CS line, CS line is configured as GPIO.
SPI Flexio master is enabled on S32k148, while SPI slave is enabled on ST HW.
We have a requirement to control the SPI slave communication based on Flexio CS line.
Such that, if CS line is only then data from the S32kMaster, should be process else treat as timeout scenario.
We are noticing that SPI CS line goes low after some delayed time.
0[04 02 14 E6 00 00 ]
010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
04 02 14 E6 00 00 <-- Payload packet to ST from S32k148
01 <-- Chip select line status of SPI Flexiomaster
00<-- Chip select line status of SPI Flexio master after certain time.
The intended request is let CS line is low for the entire Tx(S32k -> ST) and Rx(ST -> s32k) communication is complete. Since, CS line is becoming high as soon as TX being sent.. ST device is not sending any data to master considering communication has lost as CS made high because of timeout.
Would request your support to help us know how CS line can controlled.
Best Regards,
Jayakumar Appari.
Hello Jayakumar,
Where do you toggle the CS GPIO line in the code exactly?
Do you use the SDK FlexIO SPI driver?
If so, do you use blocking or non-blocking transfer functions?
If I understand the issue, it could be because you use the non-blocking functions.
Regards,
Daniel