S32K3xx Flexio UART config issue

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S32K3xx Flexio UART config issue

2,062 Views
cranes
Contributor III

Hello,

I am working on Flexio UART and the example works fine.

Now I am configuring the same thing in my project, but got different result.

1. In the example, the Flexio Uart Configuration is like this:

cranes_0-1701832386826.png

In my project, the same config is like this:

cranes_1-1701832470835.png

Do the differences in the red circles matter?

2. baud rate: In the config tool, both the example and my project are set as 115200, but in the code generated, they are different:

This is what's in the example. The divider is 12 and baud rate is 115384.

cranes_2-1701832601652.png

But in my project, the divider is 20 and the baud rate is 119047.

cranes_3-1701832759340.png

Why they different while the values are the same in the configuration tool?

3. In the example, the clock source is FRXC and Flexio clock is 48MHz. In my project the clock is PLL and the Flexio clock is 80MHz.  Is the clock difference causing the baud rate values being different as above point #2? If so, how to set the baud rate as 115200 in my project.

Right now, I am able to receive UART messages from MCU, but all are not correct symbols. I tried different baud rates in my PC to receive the UART message from MCU, all can receive messages, but no one receives correct symbols from MCU.  According to the above three differences compared to the Uart example, what might go wrong in my project?

Thanks!

Crane

 

 

 

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Crane,

There is this custom option:

danielmartynek_1-1701952217787.png

Table 129 uses division ratio of 16.

danielmartynek_0-1701951739532.png

 

Regards,

Daniel

 

 

 

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2,011 Views
cranes
Contributor III

Hi Daniel,

Tried different settings that are close to 115200, still receives unrecognized symbols. The clock is the only difference from the example. Any other settings I might missed?

Thanks!

Crane

cranes_0-1701994849509.png

(108695 in code)

cranes_1-1701994880964.png

(113636 in code)

cranes_2-1701995053130.png

(119074 in code)

 

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1,982 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hi Crane,

Can you please specify the MCU and the system clock configuration you use?

I'm asking because the FlexIO functional clock is the CORE_CLK.

And it is recommended to use one of the Clocking use case examples (RM, Section 24.7.2).

There is just on option that has CORE_CLK = 80 MHz (Option F).

Do you use Option F or your own configuration?

danielmartynek_0-1702043947752.png

If you change one clock in an example, you have to change all the clocsk accordingly.

 

Regards,

Daniel

 

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1,976 Views
cranes
Contributor III

Hi Daniel,

I am using S32K344 at 160MHz core clock and Flexio clock at 80MHz. I am not sure I am using Option F or not. How to verify?

The clock config is like this:

cranes_1-1702084347377.png

What do you mean "If you change one clock in an example, you have to change all the clock accordingly"? I am adding UART to an existing project. So I take an Uart example from RTD and make it work in my setup. Then copy all the config in the example to the existing project except the clock configuration. I need to keep the clock configuration in that project. 

Thanks!

Crane

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @cranes,

You use the Option A - High Performance mode (CORE_CLK @ 160 MHz) (Section 24.7.2.5) now.

The clock configuration is correct.

However, previously you mentioned that the FlexIO is clocked by 80MHz.

Which meant the CORE_CLK was 80MHz.

danielmartynek_0-1702289699621.png

The dividers ratios between the clocks (such as the AIPS_PLAT_CLK and CORE_CLK) must be kept.

For example, in Option A, CORE_CLK = 160MHz, AIPS_PLAT_CLK = 80MHz.

If you change CORE_CLK to 80MHz, AIPS_PLAT_CLK must be set to 40MHz and so on.

But it is recommended to use just the Options from the RM without any modification.

 

Regards,

Daniel

 

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1,917 Views
cranes
Contributor III

Hi Daniel,

So the option only depends on the CORE_CLK? So, if I want to use 160MHz, it must be Option A, right?

Now I am using CORE_CLK 160MHz and AIPS_PLAT_CLK 80MHz. Is this considered as "just the Options from the RM without any modification"?

And the result is still the same as before. 

Thanks!

Crane

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Crane,

Yes, at 160MHz CORE_CLK, we have to configure all the remaining clocks as per Opetion A (without any modification).

Regarding FlexIO, the baudrate of the emulated UART is limited by the conbination of the source clock and the FlexIO configuration. Not every baudrate is possible set precisely.

The FlexIO also allows using 2 timers to configure the baudrate (Table 444. UART transmit configuration for slow baud rate), however, the RTD driver uses just one timer (Table 443. UART transmit configuration).

 

Regards,

Daniel

 

 

 

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1,870 Views
cranes
Contributor III

Hi Daniel,

I checked all the frequency mentioned in Option A and make the changes to meet the requirement frequencies in Table 147.

cranes_1-1702580991251.png

 

cranes_0-1702580978682.png

cranes_2-1702581095115.png

cranes_3-1702581111117.png

Then I tried the baud rate 113636 and 119047

cranes_4-1702581329752.pngcranes_5-1702581442939.png

None of them works. 

How can I choose the timers? I didn't find it in the Configuration Tool.

And do you have an example of Flexio using Option A?

Thanks!

Crane

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Crane,

I have mentioned the clock options, because it looked to me that your configuration (at 80MHz) was incorrect. Which could lead to unpredictable behavior. Now, when the configuration is correct, you can forget about it.

As I said, the FlexIO baudrate connfiguration has its own limitations.

On top of that, the UART FlexIO RTD driver used just one timer for this, which is another limitation.

Why you decided to use the FlexIO instead of the dedicated LUART?

 

Regards,

Daniel

 

 

 

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1,795 Views
cranes
Contributor III

Hi Daniel,

I thought the Flexio could be simple. So I created some functions based on the example and tested them. Then I need to transfer these function to my project. At that time, I didn't realize that there are these limitations when being transferred. 

So you think it might not work in the Option A (Core clock 160MHz and Flexio clock 80MHz)? If that's the case, I have to move to LUART.

Thanks!

Crane

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1,761 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hi Crane,

The S32K3xx FlexIO works dirrectly with the CORE_CLK.

There is no option to change it.

danielmartynek_0-1703156537615.png

 

BR, Daniel

 

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1,751 Views
cranes
Contributor III

Hi Daniel,

Ok. I don't mean to change the clock to the Flexio. Just would like to confirm if it doesn't work for Flexio with the 160MHz CORE_CLOCK and 80MHz Flexio clock. If that's the case, I have to use LUART, which I don't prefer for now.

As I already designed some functions based on Flexio, I want to used them. But if it doesn't work with 160MHz core clock at all, I have to throw them away and move to LUART.

Thanks!

Crane

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello @cranes,

It depends on the source clock frequency.

It might not be possible to set it precisely.

Please have a look at the calculations in the RM, rev.7:

Table 128. FlexIO baud rate calculation (FlexIO.TIMCFGn[TIMDEC] = 101b)

Table 129. FlexIO baud rate calculation (FlexIO.TIMCFGn[TIMDEC] = 100b)

The FlexIO emulated UART configuration is described in Section 73.6.1.

 

Regards,

Daniel

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2,033 Views
cranes
Contributor III

Thanks Daniel for your reply.

Where to input the value of TIMCMPn? In the Configuration Tool, only Desire Baudrate is allowed to input a value, while the Custom Baudrate Divider and custom Baudrate Value are grayed out. It is the same as in the example.

cranes_0-1701885060383.png

In terms of calculating TIMCMPn, where to choose TIMCFGn? 

And, in the Table 129, how the TIMCMPn value is calculated? While the formula fits Table 128, it seem not fitting Table 129.

cranes_1-1701885501975.png

For example with required buad rate 19200, the theoretical baud rate is 88000000 / (256 *2 * (142+1)) = 2403.8, but the value in the table is 19230.77. 

Thanks!

Crane

 

 

 

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