S32K116 ADC - Maximum possible sampling time

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

S32K116 ADC - Maximum possible sampling time

Jump to solution
1,750 Views
markus1
Contributor II

Hello,

in order to reduce my BOM count in a current project, I would like to maximize the sampling time of the ADC. Thereby, I try to achieve that the output impedance of my temperature sensor is sufficient to drive the ADC sampling capacitor incl. analog bus capacitance.

What I already did:

1) Set ADC clock to SIRCDIV2_CLK (8 MHz)

2) Set ADC clock prescaler to 8

3) Set sample ticks to 255

This should result in a sample time of 256us.

Is there a way to further increase the sample time? E.g. using pretrigger and trigger?

Best regards,

Markus

Labels (1)
Tags (1)
0 Kudos
1 Solution
863 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hello Markus,

You would need to prescale the ADC input clock,

in this case SIRCDIV2_CLK (SCG_SIRCDIV[SIRCDIV2]).

Regards,

Daniel

View solution in original post

0 Kudos
1 Reply
864 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hello Markus,

You would need to prescale the ADC input clock,

in this case SIRCDIV2_CLK (SCG_SIRCDIV[SIRCDIV2]).

Regards,

Daniel

0 Kudos