S32K ICU example project ISR mapping issue

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S32K ICU example project ISR mapping issue

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bbaskii
Contributor II

Hi NXP Team,

For a specific use case I wanted to enable and use ICU ISR (SIUL2_EXT_IRQ_24_31_ISR) in S32K342 bootloader project. But I unable find the mapping of IRQ and ISR handler in the example project which i want emulate in bootloader by following the same steps. I found that IRQ configuration are in IntCtrl_Ip_Cfg.c file and it is placed in mcal_const_cfg both flash and sram linker files. But I unable to find the link from there to intc_table in Vector_Table.s file where the interrupt vector table is placed. Can you please point me to any document which explains this or If you could tell me it would be great help to complete an pending task.

Looking forward your assistance here.

Thanks In Advance,

bbaskii

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NamLe
NXP Employee
NXP Employee
Hi bbaskii,
I think you want to understand how to map Irq and Isr with Vector_table, so i will give you an explaination.
As you said, you already found the Irq in file IntCtrl_Ip_Cfg.c, that's correct. You can see we have SuiL Irq from no.53 to 56, which is matching with Interrupt Mapping (attachment from RM), and for Instance 24-31 i'll use SIUL_3_IRQn.
Next we have to map this Irq with Isr (like a callback function), so we have the Platform function doing this
Install_Siul2_ISR.png
As you can see inside RTD driver, after calling this function, the Isr with corresponding number as Irq will be mapped into Vector_Table through the address that specified defined for chip.
Set_ISR_to_IVT.png
The start address of Interrupt vector table addressed in VTOR register, which follow Cortex M specs. 
Interrupt_vector_table_addr.png
As you can find, in linker file will contain address of intc_vector, which start in specified address, for example int_pflash area.
intc_table_addr.png
And the address of Vector Table will match here.
Vector_Table_addr.png
So that is how ISR works in processing, as you can try to read Platform's functions for those Irq Handler.
Please let me know if you have further questions.
Thank you,
Nam.
 

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NamLe
NXP Employee
NXP Employee
Hi bbaskii,
I think you want to understand how to map Irq and Isr with Vector_table, so i will give you an explaination.
As you said, you already found the Irq in file IntCtrl_Ip_Cfg.c, that's correct. You can see we have SuiL Irq from no.53 to 56, which is matching with Interrupt Mapping (attachment from RM), and for Instance 24-31 i'll use SIUL_3_IRQn.
Next we have to map this Irq with Isr (like a callback function), so we have the Platform function doing this
Install_Siul2_ISR.png
As you can see inside RTD driver, after calling this function, the Isr with corresponding number as Irq will be mapped into Vector_Table through the address that specified defined for chip.
Set_ISR_to_IVT.png
The start address of Interrupt vector table addressed in VTOR register, which follow Cortex M specs. 
Interrupt_vector_table_addr.png
As you can find, in linker file will contain address of intc_vector, which start in specified address, for example int_pflash area.
intc_table_addr.png
And the address of Vector Table will match here.
Vector_Table_addr.png
So that is how ISR works in processing, as you can try to read Platform's functions for those Irq Handler.
Please let me know if you have further questions.
Thank you,
Nam.
 
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Mehul_Patel_NXP
NXP Employee
NXP Employee

Hi, @bbaskii , 

 

Please let us if any further issue with your case. Or can we close the ticket. 

 

Thank you. Best regards. 

 

- Mehul Patel 

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