Interrupt api is not called in case of SMR Verification is Periodic in S32K3

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Interrupt api is not called in case of SMR Verification is Periodic in S32K3

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HyunungPark1
Contributor III

Hi.

Interrupt api is not called in case of SMR Verification is Periodic in S32K3.

Could you please let me know why Interrupt api is not called?

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nxf78987
NXP Employee
NXP Employee

Hello @HyunungPark1,

Sorry for my late response.

Did you check the below bits in your program?

NVIC->ISER6 bit 4: Set if you enabled MU0 interrupt.
NVIC->IABR6 bit 4: Set if iMU0 interrupt occurred.
 
Best regards,
Dan

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nxf78987
NXP Employee
NXP Employee

Hello @HyunungPark1,

Could you send me the code implemented in the CDD_InitFTDConfiguration() function and Fls configuration?

And what is the HSE Firmware you are using?

Best regards,

Dan

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HyunungPark1
Contributor III

Hi.

below is the information for RTD and HSE Firmware which  I used

RTD : SW32K3_RTD_4.4_R21-11_3.0.0_P01_HF02
 
HSE FW : s32k3x4_hse_fw_0.5.0_2.1.0_pb220625.bin.pink
 
and below is the procedure and code for smr verifiation - peridoc 
 
============ CDD_InitFTDConfiguration ============= 
 
#define RSA_TAG_FTD_SIGNATURE_FLASH_ADDRESS 0x10000400UL
 
g_smrEntry[smrIndex].configFlags = HSE_SMR_CFG_FLAG_QSPI_FLASH ;
g_smrEntry[smrIndex].pSmrDest = 0x20430000;
g_smrEntry[smrIndex].checkPeriod = 100;
g_smrEntry[smrIndex].pSmrsrc=0x0046c000;
g_smrEntry[smrIndex].smrSize = 256;
g_smrEntry[smrIndex].authKeyHandle = CRYPTO_KEY_ID_NVM_FTD_PUBLICKEY_HANDLE;
g_smrEntry[smrIndex].authScheme.sigScheme.signSch = HSE_SIGN_RSASSA_PKCS1_V15;
g_smrEntry[smrIndex].authScheme.sigScheme.sch.rsaPkcs1v15.hashAlgo = HSE_HASH_ALGO_SHA2_256;
g_smrEntry[smrIndex].pInstAuthTag[0] = RSA_TAG_FTD_SIGNATURE_FLASH_ADDRESS; 
g_smrEntry[smrIndex].pInstAuthTag[1] = (uint32_t)NULL;
 
============ the procedure ============= 
1. IntCtrl_Ip_InstallHandler(HSE_MU0_ORED_IRQn, &Mu_Ip_Mu0_OredGP_Isr, NULL_PTR); 
    -> Install ORed GP interrupt for MU-0
 
2. IntCtrl_Ip_EnableIrq(HSE_MU0_ORED_IRQn) 
    -> Enable ORed GP interrupt for MU-0
 
3. Hse_Ip_RegisterGenericCallback(Crypto_aPartitionToMuMapping[0].u8MuInstance, u32NotifEventsMask, GenericPurposeCallback)
   -> Registers a general purpose callback
 
4.  Status   = CDD_InitSBConfiguration(...)
   -> Set configuration for SMR Verification-Boot
 
5. Status = CDD_InitFTDConfiguration(...)
   -> Set configuration for SMR Verification - Periodic
 
6.  Reset Device
 
7.  Change the firmware using Fls_Erase and Fls_Write ap
 
==> The below is not called
     ISR(Mu_Ip_Mu0_OredGP_Isr)
     {
     Hse_Ip_GeneralPurposeIrqHandler(0U);
      }
 
BRs.
Hyunung Park
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HyunungPark1
Contributor III

Hi.

below is the information for RTD and HSE Firmware which  I used

RTD : SW32K3_RTD_4.4_R21-11_3.0.0_P01_HF02
 
HSE FW : s32k3x4_hse_fw_0.5.0_2.1.0_pb220625.bin.pink
 
and below is the procedure and code for smr verifiation - peridoc 
 
============ CDD_InitFTDConfiguration ============= 
 
#define RSA_TAG_FTD_SIGNATURE_FLASH_ADDRESS 0x10000400UL
 
g_smrEntry[smrIndex].configFlags = HSE_SMR_CFG_FLAG_QSPI_FLASH ;
g_smrEntry[smrIndex].pSmrDest = 0x20430000;
g_smrEntry[smrIndex].checkPeriod = 100;
g_smrEntry[smrIndex].pSmrsrc=0x0046c000;
g_smrEntry[smrIndex].smrSize = 256;
g_smrEntry[smrIndex].authKeyHandle = CRYPTO_KEY_ID_NVM_FTD_PUBLICKEY_HANDLE;
g_smrEntry[smrIndex].authScheme.sigScheme.signSch = HSE_SIGN_RSASSA_PKCS1_V15;
g_smrEntry[smrIndex].authScheme.sigScheme.sch.rsaPkcs1v15.hashAlgo = HSE_HASH_ALGO_SHA2_256;
g_smrEntry[smrIndex].pInstAuthTag[0] = RSA_TAG_FTD_SIGNATURE_FLASH_ADDRESS; 
g_smrEntry[smrIndex].pInstAuthTag[1] = (uint32_t)NULL;
 
============ the procedure ============= 
1. IntCtrl_Ip_InstallHandler(HSE_MU0_ORED_IRQn, &Mu_Ip_Mu0_OredGP_Isr, NULL_PTR); 
    -> Install ORed GP interrupt for MU-0
 
2. IntCtrl_Ip_EnableIrq(HSE_MU0_ORED_IRQn) 
    -> Enable ORed GP interrupt for MU-0
 
3. Hse_Ip_RegisterGenericCallback(Crypto_aPartitionToMuMapping[0].u8MuInstance, u32NotifEventsMask, GenericPurposeCallback)
   -> Registers a general purpose callback
 
4.  Status   = CDD_InitSBConfiguration(...)
   -> Set configuration for SMR Verification-Boot
 
5. Status = CDD_InitFTDConfiguration(...)
   -> Set configuration for SMR Verification - Periodic
 
6.  Reset Device
 
7.  Change the firmware using Fls_Erase and Fls_Write ap
 
==> The below is not called
     ISR(Mu_Ip_Mu0_OredGP_Isr)
     {
     Hse_Ip_GeneralPurposeIrqHandler(0U);
      }
 
BRs.
Hyunung Park
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nxf78987
NXP Employee
NXP Employee

Hello @HyunungPark1,

I saw that you have not called "Hse_Ip_Init(MU0_INSTANCE_U8, &HseIp_MuState);" in your code to init MU_0.

So, you need to call "Hse_Ip_GetHseStatus(MU0_INSTANCE_U8);" and "Hse_Ip_Init(MU0_INSTANCE_U8, &HseIp_MuState);" after "IntCtrl_Ip_EnableIrq(HSE_MU0_ORED_IRQn);"

Best regards,

Dan

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HyunungPark1
Contributor III
Hi
 
my code call Hse_Ip_Init like below code
 
/* Install ORed GP interrupt for MU-0 */
  IntCtrl_Ip_InstallHandler(HSE_MU0_ORED_IRQn, &Mu_Ip_Mu0_OredGP_Isr, NULL_PTR);
 
  /* Enable ORed RX interrupt for MU-0 */
  IntCtrl_Ip_EnableIrq(HSE_MU0_ORED_IRQn);
 
/* Initialize Crypto driver */
Crypto_Init(NULL_PTR); ==> Hse_Ip_Init is called by this api
 
RetVal = Crypto_GetAttribute(HSE_SECURE_LIFECYCLE_ATTR_ID,sizeof(hseAttrSecureLifecycle_t) ,(void *)&gHseCurrentLC);
 
if(RetVal == E_OK && (gHseCurrentLC & HSE_LC_CUST_DEL == HSE_LC_CUST_DEL)){
RetVal = CDD_CheckKeyProvisioning();
if(RetVal == E_NOT_OK){
/* Format HSE key catalogs (RAM + NVM) */
RetVal = Crypto_Exts_FormatKeyCatalogs();
//CDDAssert((Std_ReturnType)E_OK == RetVal);
}else{
}
}else{
RetVal = E_OK;
}
Hse_Ip_RegisterGenericCallback(Crypto_aPartitionToMuMapping[0].u8MuInstance, u32NotifEventsMask, GenericPurposeCallback);
return RetVal;
 
BRs.
Hyunung Park
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HyunungPark1
Contributor III

Hi

This issue is not resoived.

Hyunung Park

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nxf78987
NXP Employee
NXP Employee

Hello @HyunungPark1,

I have a question: when you perform step 6 (Reset Device) then after that: Is your program run step 1 to 5 again?

Best regards,

Dan

 

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HyunungPark1
Contributor III

Hello Dan

My program doesn't run step 1 to 5 again after step 6 (Reset Device) 

Best Regards.

Hyunung Park

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nxf78987
NXP Employee
NXP Employee

Hello @HyunungPark1,

If your program doesn't run step 1 to 5 again after step 6 (Reset Device) then it mean the value of registers was reset and indicated that HSE_MU0_ORED interrupt was not enable when you perform test.

Best regards,

Dan

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HyunungPark1
Contributor III

Hello Dan.

I think that HSE_MU0_ORED interrupt is enable because the below code is performed after device reset

/* Install ORed GP interrupt for MU-0 */
IntCtrl_Ip_InstallHandler(HSE_MU0_ORED_IRQn, &Mu_Ip_Mu0_OredGP_Isr, NULL_PTR);

/* Enable ORed RX interrupt for MU-0 */
IntCtrl_Ip_EnableIrq(HSE_MU0_ORED_IRQn);

Best Regards.

Hyunung Park

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nxf78987
NXP Employee
NXP Employee

Hello @HyunungPark1,

Sorry for my late response.

Did you check the below bits in your program?

NVIC->ISER6 bit 4: Set if you enabled MU0 interrupt.
NVIC->IABR6 bit 4: Set if iMU0 interrupt occurred.
 
Best regards,
Dan
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HyunungPark1
Contributor III

Hi.

This issue is resloved.

Hyunung Park