How to set ADC mux_mode GPR register in EB tresos?

[IvyGuo]

According to user manul said: ADC2 S8 is driven by GPIO_PAD133 (default) and GPIO_PAD45 (mux_mode). but how to and where to set the DCM register in EB Tresos studio？ I can not find it in Platform Mcl Mcu and other likely modules?

Platform：RTD2.0，ASR4.4 EB Tresos 28

[Robin_Shen]

Hi

Please refer to the discussion in S32K344 ADC: HAS_ADC_INTERLEAVE problem

Sorry for the inconvenience we bring you!

Best Regards,
Robin
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[IvyGuo]

Hi，Robin：We found it fixed in RTD2.03，We used RTD2.03 ,  But in RTD2.03 release note，just mentioned ADC2_S9，I assumed ADC2_S8 has the similar problem. Right? 

[Robin_Shen · Accepted solution]

Sorry. As far as I know, this DCMRWF4 related bug was fixed in S32K3 RTD 3.0.0. It should be clear after checking the Siul2_Port_Ip_WriteDCMConfiguration. 

Sorry for causing confusion, the RTD release note only excerpts the bug description of the internal system and does not include the detailed information of the bug. So ADC2_S8 also has problems.

Did you configure the pin in PortContainer?

[IvyGuo]

The proble  solved if I configured in PortContainer.