When triggering DMA, if the source address is in flash or RAM space, but the destination address is in a peripheral register, it will result in inaccurate capacitance collection for touch sense.
If the DMA destination address is in Flash or RAM, the above phenomenon will not occur.
Touch sense note see attatchment
Hello @LijieDu,
What S32K part is it?
And which peripheral register do you mean?
There could be issues with the arbitration on the crossbar switch.
Do you use Fixed priority or Round robin?
Regards,
Daniel
Sorry for the late reply.
I use s32k118, and generate waveforms with different duty cycles through FTM PWM mechanism.
So I use DMA chnl2 to periodically update the FTMx->Controls [chnl]. CnV register of FTM.
DMA chnl0 and chnl1 are used to tx and rx in spi moudle.
And round robin arbitration is used for channel selection.
Hi @LijieDu,
The eDMA has its own arbitration control (CR[RECA]).
And there is arbitration on the crossbar switch too:
have you set CBRR = 1.
BR, Daniel
I have set CBRR to 1, and it has no improvement.
The left side of the figure shows the measured values when the DMA destination address is set to the peripheral register.
The right side of the figure shows the measured values when the DMA destination address is set to the RAM space.
Only difference is destination address.
Can you elaborate on the description of the image? What each graph means?
Anyway, regardless of the arbitration, the peripherals can be access either by the eDMA or the Core at a time. And this can cause issues if the core frequently access the peripherals.
Do you use the highest system clock frequency?
Thanks,
Daniel
SysClk is 48MHz.
DMA trigger frequency is about 30khz(trigger DMA function every 33us), duration is about 30ms when enable DMA transfer function.
The description of the image:
Picture above shows: Measured values when the DMA destination address is set to the peripheral register and DMA is triggered in real time. We can see that the values get from ADC is unstable.
Picture above shows: Measured values when the DMA destination address is set to the RAM space and DMA is triggered in real time. We can see that the values get from ADC is stable.
I see, thank you.
Have you tried using a different pin for the PWM output?
BR, Daniel
I can have a try.
More description in detail:
I use 7 ADC channels (ADC0_SE3/ADC0_SE5/ADC0_SE6/ADC0_SE9/ADC0_SE12/ADC0_SE13/ADC0_SE14) to sample touch sense key. Same problem occurs in every channel.
Hi @LijieDu,
There can be two issues, and we have already touched on that.
The DMA concept cannot be exactly deterministic, becasue the Core and the eDMA access the same resources through the crossbar switch and the peripheral bridge.
Before the GPIO pins are switched to High-Z, the ADC sampling already starts (1) to removed any remaining charge in the ADC sample and hold capacitor.
1. ADC is triggered
2. GPIO in HIGH-Z
X. Sample ends (pin disconnected from ADC), conversion starts
3. Converion ends
If the ADC is triggered (1) with some delay due to arbitration, the sample phase starts and ends in different poinst, and this leads to incorrect measurement.
Can you try with a longer Sample time?
Do you use DMA to trigger the ADC conversions too?
The high freq. PWM signal should not be at a pin adjacent to the touch sense pins (and traces).
Regards,
Daniel
I have tried to use different pin to generate pwm.
it doesn't work.
I have tried to make sample time longer(make it 1us and 2us).
it doesn't work.
/(ㄒoㄒ)/~~
Can you try with a longer Sample time?
Yes, I can try.
Do you use DMA to trigger the ADC conversions too?
No, only in spi and pwm out.
I have been on a business trip these past two days, so I don't have time to try. I will test and provide feedback on the results as soon as possible.
I didn't set the bit to 1.
I can have a try and give you feedback on the results later.