S32G PCIe Question

[Coco111]

I am a novice PCIe user and I would like to know the following questions:

1. How to test PCIe?

2. How to read and write PCIe (when two development boards are interconnected through PCIe cables and configured as RC and EP respectively)?

3. How to support NTB?

[Daniel-Aguirre]

Hi,

There is an example available for PCIe, still, the requirements are having an EVB and an RDB board for making it work.

The example is available under the following path:

"C:\nxp\S32DS.3.4\S32DS\software\PlatformSDK_S32XX_2022_03\SW32_RTD_4_4_3_0_2_D2203\Pcie_TS_T40D11M30I2R0\examples\EBT\Pcie_Example_EBT_S32G274A_M7_001"

The path could vary depending on the specific installation of the RTD plugins. In there, the EB Tresos project is provided, as well as the steps to follow in order to enable PCIe communication between an EVB and an RDB ("readme.txt" file).

As for supporting NTB, we are not seeing anything on regards of the specific function under the provided driver. We do apologize.

Please, let us know.

[Coco111]

Thank you for your reply. I'm sorry I didn't explain it clearly.

What I want to know is the usage in the Linux development environment

[Daniel-Aguirre]

Hi,

Thanks for your feedback.

The only information it seems to be available for PCIe under Linux is the one provided under Chapter 9 of the BSP36.0 User Manual for S32G2 platforms. Also, Linux usage is provided under the M7 example, since one of the boards will use Linux for communication.

Aside from the previously mentioned information, we did not find anything else. We do apologize.

Please, let us know.

[Coco111]

Thanks for your help.

but  I can only obtain the bsp35 user manual. please tell me  how get the bsp36 user manual?

[Daniel-Aguirre]

Hi,

BSP35.0 also has the previously mentioned chapter 9 for PCIe support [Page 65, BSP35.0 User Manual Updated] under the provided User Manual.

As for BSP36.0, it seems that you are not provided with access to that specific release. If you would like to access it, help us contacting your local NXP representative/FAE, for them to start the process of providing you with the required access.

Please, let us know.

[Coco111]

As we can see, the content of the document is     "enable", "scan", and "msi interrupt",
But my question is how users can use PCIe to send/receive data

 (such as communication between two SoCs).

[Daniel-Aguirre]

HI,

Thanks for you feedback. Then, the EB Tresos example is the only documentation available on this regards. The following is told under the "readme.txt" attached to the example:

"Memory transaction are already enabled by the s32gep.ko module so you can start to read and write in the endpoint shared memory. For example:
Read:
devmem2 0x4800100000
Write:
devmem2 0x4800100000 w 0x12345678
Note that the addresses from the examples above are in the range displayed by the lspci command."

The above-mentioned module is provided under the EB Tresos example.

Please, let us know.

[Coco111]

I am busy testing the network, and I will handle it later