PWM interrupt not hitting

[Hareesh]

Hi NXP team,

We are using S32K344 EVK board and s32 design studio 3.5 .

We need to generate a PWM signal and generate the interrupts on both leading and falling edges of the pulse.

Is there any sample code in the SDK to do this one?

Although we are able to generate the PWM signal, but we are unable to generate the interrupt.

Please assist me in fixing this problem.

Best regards,

Hareesh

[Hareesh]

Hi,

Could someone please assist me in resolving this problem?

Best regards,

Hareesh

[Robin_Shen]

Hi Hareesh,

I'm sorry for the delay, I have been overloaded the last couple of days.

Please add the following function to the test project you sent me:
Emios_Pwm_Ip_SetFlagRequest(INSTANCE_0, CHANNEL_2, EMIOS_PWM_IP_INTERRUPT_REQUEST);

Best Regards,
Robin
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[Akhil1]

Hi @Robin_Shen ,

I am also working on PWM interrupt in s32K3, can you please provide the sample code for it

Thanks Akhil

[Hareesh]

Hi @Robin_Shen ,

Thanks for the update.

After adding that function, the PWM ISR is working properly.

However, how can we distinguish between leading-edge and trailing-edge events in the ISR?

Is there any event checking for both edges of the pulse?

Best regards,

Hareesh

[Akhil1]

Hi @Hareesh ,

I am also working on PWM interrupt, can you please send me the sample code

Thanks Akhil

[Hareesh]

Hi @Akhil1 ,

Please find the attached file for example code.

Best regards,

Hareesh 

[Dev15]

@Hareesh ,

The project is not available to download. Please upload the pwm working ISR project.

Thank you

[Akhil1]

Hi @Hareesh ,

Thank you for your support..It is working fine.

Regards

Akhil

[Robin_Shen]

Try to read the voltage level of the PWM output pin in the ISR.

[Hareesh]

Hi @Robin_Shen ,

For the OPWFMB mode (variable frequency and variable duty cycle), we require a PWM frequency of 0.5 Hz.

The system clock and ADC clock will both decrease if the EMIOS module frequency is lowered to achieve lower frequency PWM because both have the same source clock (CORE_CLK) (Please refer the attached screenshot).

Is it feasible to switch the EMIOS module's clock source from CORE_CLK? If so, how should it be done?

If we set the CORE_CLK = 20 MHz,

EMIOS_CLK = 20M / 16(Clock Prescaler) = 1.25 MHz

Period [in ticks] = EMIOS_CLK / PWM in Hz

PWM in Hz = EMIOS_CLK / Period [in ticks]

PWM in Hz = 1.25 MHz / 65535 (The maximum value we can set in S32 DS IDE)

PWM in Hz = 19.07 HZ

Thus, we will only obtain a minimum PWM frequency of 19.07 Hz when we use the maximum clock prescaler and period value combinations.

In order to get a PWM frequency of 0.5 Hz in OPWFMB mode, what setups are required?

Best regards,

Hareesh

[Robin_Shen · Accepted solution]

Please ask a new question if you have any questions that are not related to the original topic of an existing case. It helps to keep it clear. Thank you for your understanding.