PLL & mc9s12xdt512

[Eric_t]

Hello

I am going to use to mc9s12xdt512 without PLL support.

The manual mensions that "If PLL usage is not required, the XFC pin must be tied
to VDDPLL." 

The same reference is made for mc9s12dg256. In a forum discussion a few years ago, it turned out that this was an error in the document and that the XFC pin must be connected to VDDPLL via a 4K7 resistor.
I assume that in the case of the mc9s12xdt512 it is also an error in the document and that in the mc9s12xdt512 the XFC pin must also be connected to VDDPLL via a 4K7 resistor.
Can anyone confirm this?

[lama · Accepted solution]

Hi,

I have found an answer I provided in 2010 after discussion with the design team. Both solutions are OK....but...


"

The reason why this resistor is recommended is that we want to avoid that the XFC input goes to too low value. When the PLL is off, it would not matter since XFC is internally pulled to VDDPLL. However we do release the XFC just after reset (because the PLL is enabled and tries to multiply the oscillator up). In this short phase until the software turns the PLL down again, XFC voltage could collapse (the chargepump could pull it down pretty easy against no load on the board), such the VCO may go to very high frequency. If in this case a clock monitor event would happen (or even the lock sensor might be misleaded), the high frequency of the VCO could adversely affect the operation of the mcu.

You see the if, if, if so it is not too likely that actually bad things may happen, but it is not totally bullet proof either. That's why a resistor or even a short to VDDPLL is recommended.

"

Best regards,

Ladislav