on the fly chop mode of P2020 DDR controler

[yansongzhu]

I will use DDR3 on the P2020 platform. But I have noticed that the DDR controler must be setted in 8-beat burst mode when using 32-bit bus mode and in 4-beat burst mode when using 64-bit bus mode with DDR_SDRAM_CFG[8_BE]. So, I have some question.

Q1: Is that because the cache lines on the e500 core are 32 bytes wide ? So the burst length multiplied bus wide must equals 32bytes ?

Q2: When I using 64-bit bus mode with DDR_SDRAM_CFG[8_BE] = 0 and DDR_SDRAM_CFG_2[OBC_CFG] = 1, does it mean that the DDR controler can access the DDR3 by using BL8 or BC4 ? If that is true, how to explain the Q1 ?

Q3: When I using 64-bit bus mode with DDR_SDRAM_CFG[8_BE] = 0 and DDR_SDRAM_CFG_2[OBC_CFG] = 0, does it mean that the DDR controler can access the DDR3 only by using BC4 ?

Q4: If the DDR3 only can be accessed by 4-beat burst length once on P2020 platform, does it mean that the performance of 64-bit bus mode is not much higher than the performance of 32-bit bus mode ?

Q5: When I use the ECC function in 32-bit bus mode, is the MDQ[32]~MDQ[39] used as the ECC[0]~ECC[7] ? 

[ufedor]

1) Your understanding is correct.

2-3) Please refer to the AN4039 - PowerQUICC and QorIQ DDR3 settings, Table 9, 8_BE:

"For all PowerQUICC/QorIQ parts other than P4080:
• If a 64-bit data bus is used (that is, DDR_SDRAM_CFG[DBW] = 00,) then this field must be set to 0 (4-beat burst).
• If a 32-bit data bus is used, then this field should be set to 1 (8-beat burst).
• If a 16-bit data bus option is available and used, this field should be set to 1 (8-beat burst).
For P4080 parts:
• This field should be set to 1 (8-beat burst)."

4) Your assumption is reasonable for single 32-bit or 32-byte accesses, but in case of DMA transfers the 64-bit performance is doubled comparing to the 32-bit one.

5) MECC[0:7] are used as ECC data byte for any bus width.

[yansongzhu]

Thank you !

I have read the AN4039. I'm not wondering about the DDR_SDRAM_CFG[8_BE], but the DDR_SDRAM_CFG_2[OBC_CFG].

According to your answer, can I suppose that when DDR_SDRAM_CFG_2[OBC_CFG] = 1, the DDR controler access the DDR3 with BL8 in case of DMA transfers, but with BC4 in case of cache transfers ?