What is the timing associated with the IFC Transceiver Enable pin?

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What is the timing associated with the IFC Transceiver Enable pin?

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scottgerhold
Contributor II

The QorIQ processor provide a Transceiver Enable pin to support fast/slow memories on the bus. But I cannot find anything in the documentation that details the timings for that signal - such as when does it actually get enabled during a transaction. Is it asserted as soon as ALE is asserted with the address for the transaction? When does it deassert - this is needed for controlling bus turn-around time. In particular I am interested in the T2080's implementation.

Please let me know where to look for this information.

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scottgerhold
Contributor II

Ok, so if I have 3 IFC_CSx that are on the slow side of the transceiver, their timing will drive the enable signal appropriately. Thus saving me a 3-input AND gate. Thus the IFC_BCTL signal is still used to control the direction and it accounts for turn-around time concerns?

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ufedor
NXP TechSupport
NXP TechSupport

Correct.

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ufedor
NXP TechSupport
NXP TechSupport

IFC_TE has the same timing as IFC_CS.

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