I am using T1022 in my design, I want to know what size of antipad will i use on DDR4 DQS lanes and Clock lanes. and also on PCIe and SGMII lanes. Is 28 mil antipads is right?
Thanks for Pad stack details.
In suggested Reference file also, I am unable to find any antipads .
The problem with 32 mil antipad is, we are loosing ground reference to signals.
BGA pitch in T1022 is 31.5.
Regards,
RAM PAL SINGH
All requested information can be obtained from the "T104xD4RDB_revA.brd"
In reference Board files of T1042, there are no antipads in REV PA. However in T1040 reference board rev0 file, 26 mils antipads are drawn. what to do.
The Design package is:
https://www.nxp.com/downloads/en/printed-circuit-boards/T1042D4RDB-PA_DF.zip
The file in the package is "T104xD4RDB_revA.brd"
The padstack for the V20D10 is:
It is reasonable to refer to the PCB layout of T1042D4RDB-PA provided in Design Files available at:
QorIQ® T1040 Reference Design Board | NXP
Padstack name: V20D10
drill: 10
pad: 20
antipad: 32