P2020RDB: Why are the DDR3 data lines not connected in order?

[sean_simon]

Hello all,

I am working on a design using the P2020 QorIQ processor and DDR3 memory. 

As a reference, I am using the P2020 reference design board schematic if I have any questions. I have attached it.

My main question revolves around the DDR3 Memory interface on page 3 of the attachment.

They are utilizing all 64 data lines on the processor and are using four x16 bit DDR3 parts. What I'm confused about is the way they routed the signals. Instead of connecting the lines in numerical order (MDQ00 ->DQ0 & MDQ01 ->DQ1) they connect it in a seemingly random order (MDQ06->DQ0 , MDQ00->DQ1, MDQ07->DQ3 and so on). 

Can anyone provide an explination for why they did this?

Thanks in advance!

[ufedor]

Please refer to the AN3940 - Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces, Table 1. DDR3 designer checklist, Discrete memory topologies, 45:

"When placing components, optimize placement of the discretes to favor the data bus (analogous to DIMM topologies).
Optional: Pin-swap within a given byte lane to optimize the data bus routes further.
Caution: Do not swap individual data bits across different byte lanes."