How to bring up the DDR controller in the LS1046A?

[gaborkocsis]

We have made our custom board based on a LS1046A with 4 GByte on-board DDR4 memory
(MT40A512M16HA-083E).

We have been struggling for a week to bring up the DDR controller, but it doesn't work.

We use CodeWarrior and QCVS validation Tool and CodeWarrior Tap.

In CodeWarrior's Debug section I run the Connection Diagnostics. It runs through OK, but at the last item that tests DDR memory access fails with message "Cannot read from address 0x80000000".

I've tried the Memory Validation Tool, but it failes as well trying any test of them.

The error message is "Validation cannot proceed due to other DDR hardware or software issues". The ERR_DETECT register's ACE bit is set. (This bit's meaning is Automatic Calibration Error).

Does anybody have experience with DDR controller bring up or idea what can the problem be?

[addiyi]

The easiest way is to use DDR Validation tool to find and optimize the DDR configuration.

Adrian

[gaborkocsis]

Yes, I understand, but the validation tool fails and I don't know where shall I look for my mistake. I've checked the clock, reset, supply voltage, they're OK. ERR_DETECT ACE bit. Automatic Calibration Error. What does it mean?

[addiyi]

If ACE bit is set in ERR_DETECT register, then initialization related to write leveling has failed. What is the results when running first table in Centering the clock? Do you have DRAM_RESET asserted and de-asserted with HRESET?

Adrian

[gaborkocsis]

Good morning, thank you for your answer.

Yes, the DRAM_RESET and HRESET asserted/de-asserted together.

When running "Centering the Clock" the "Auto search & detect.." table's single cell blinks in blue a while then changes to yellow and the in the "Test results' Summary" is written that "The validation cannot proceed due to other DDR hardware or software issues" The others like CLK adjust value and WRLVL margin don't run.

regards,

Gabor

[yipingwang]

DDR_ERR_DETECT[ACE] can be set due to the following reasons:

1. The training sequence that the controller follows to calibrate the read data path was not able to complete. This would probably only happen if there was a hard failure on the memory interface caused by board-level issues or incorrect controller settings.
   

2. Incorrect termination of MDICx signals.

3. Write leveling calibration was not able to complete. This relates to improper settings of the DDR_WRLVL_CNTL register or board-level issues.

For the DDR controller initial parameters configuration in QCVS project, please use read from SPD method or create a default QCVS project and configure DDR related properties according to the DDR datasheet.

Have a great day,
TIC

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