BRI over TDM in P1021

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BRI over TDM in P1021

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ibram
Contributor I

Hi,

I am trying to bring BRI interface using P1021 QUICC's TDM with the help of S/T transceiver. I have following doubts:

1. what is the use of TSYNC and RSYNC signals of TDM interface?

2. should i have external circuitry for Dataclock(DCL) and FrameSync to connect multiple S/T transceiver on the same TDM bus?

3. Planning to use SPI for control and status information transfer. Is that ok?

Please help me to clarify these doubts.

Thanks in advance.

Regards,

Ibram

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3 Replies

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r8070z
NXP Employee
NXP Employee

1) TSYNC and RSYNC are essential signals of P1021 TDM interface. They define the TDM frame. You can find comprehensive description of the TDM interface in “Overview” section of Chapter 22 “Serial Interface with Time-Slot Assigner” in the QUICC Engine Block Reference Manual with Protocol Interworking, Rev. 5. You can download manual from Freescale site (http://www.freescale.com/).

2) P1021 TDM only works with an external sync and external clock.

3) Yes it is ok. The P1021 has SPI controllers. By the way see 22.9.4 “IDL Interface Example ” in the QUICC Engine Block Reference Manual with Protocol Interworking, Rev. 5. In this example the SPI sends initialization commands and periodically checks status from the S/T transceiver.

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ibram
Contributor I

Thanks for your response.

I would require some more clarification on it.

1. can we connect Externally generated frame sync to TSYNC and RSYNC pins of the P1021?

2.How do we connect Externally generated CLK to P1021? which pin should be selected?

Also please direct with the link of downloading QUICC Engine Block Reference Manual with Protocol Interworking, Rev. 5, as i am not able to find this document.

Thanks in advance.

Regards,

Ibram

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r8070z
NXP Employee
NXP Employee

1) Yes, even more - you have to connect external sync signals.

2) There are special registers which selects clock sources for TDM and configure I/O pin. QUICC Engine Block Reference Manual describes that in  chapter 5.5.2 CMX SI1 Clock Route Low Register (CMXSI1CRL). Its Table 5-6 shows the clock source options for the serial controllers and TDM channels for the P1021, P1012. (CLKn)

Then you should look into chapter 3.5 Parallel I/O ports in the P1021 reference manual in order to get which parallel port pin belong to this clock source (CLKn).

Use search field on the fresscale.com page (on top right) in order to get download link.

Insert QEIWRM.PDF into search field and click on search sign  or press Enter and it provide you link to the manual in the first string of search result.

In the same way for p1021 reference manual use P1021RM.PDF as search keyword.