Hi All,
Recently we received an errata (CPU A-005125) from freescale, in which a workaround is given for resolving a system hang issue of e500 core. It is recomended to set SPR976[40:41] to b'10. However, we can not found this register in the PowerPC e500 Core Family Reference Manual.So could anybody please tell me what's the name of this SPR or how can I find it in any datasheet?
What's more, for the system hang, could anybody kindly tell me how to reproduce this issue? Thanks a lot.
-Kris.
已解决! 转到解答。
You are right. The description of SPR976 is not available in e500v2 manual.This should be done as early as possible. Hence this has to be in the u-boot boot-up stage.
Hi Suchit,
That is to say we can not find the description of the SPR976 in the specs, right? In this case, is it correct to write b'10 to the SPR976[40:41] in the u-boot boot-up stage? or in the runtime (say, Linux) stage?
Thanks,
-Kris.
As the erratum says, the issue may occur while there are some transactions on PCI/PCIe/SRIO bus (for more details, please refer the erratum). If you are confident that there will be no transactions on PCI/PCIe/SRIO bus till Linux comes up, you may choose to apply workaround in Linux.
For example, the u-boot bootloader scans the PCI/PCIe bus and accordingly creates in/out bound windows. The system may hit the erratum if PCI/PCIe transactions start before Linux comes up.
Hi Kris,
I am also in your boat ! Need to implement this bit setting. But as you mentioned I am not able to see the possible way we can define this register in code. I see people have suggested to implement it in u-boot. Could you please elaborate more on this ? Is there no way to define this in code ?
BTW, I am working for a router.