Are the bank address bits of the mode register settings (two msb's) of each field in DDR_SDRAM_MODE and DDR_SDRAM_MODE_2 used by the DDR controller at initialization or are they ignored? There is a separate field for each specific mode register, which should allow the bank address bits to be ignored when addressing the DRAMs. We're trying to assess the impact of a SW bug that incorrectly set the two msb's of the ESDMODE, ESDMODE2, and ESDMODE3 fields. Would these to bits be ignored or cause incorrect DRAM mode register writes?
