Hi,
I was hoping someone can verify/clarify some passages from the datasheet (Rev. 7).
Passage
12.3: When DFS enabled, the FS state machine monitors and counts faults happening.
Question
Passage
12.5.3: The fault error counter is incremented by 1, each time RSTB and/or FS0B pin is asserted. When FS0B is asserted, the fault error counter is incremented by 1, every time the watchdog error counter maximum value is reached.
Question
Passage
12.7.1.6 and 12.7.2.4: The overvoltage detection switches off the regulator.
Question
Regarding the disabling of the regulator; is it permanently switched off, until the next Wake-up or POR?
I hope I have understood these passages correctly, but I would like to verify.
Kind regards,
Joey
解決済! 解決策の投稿を見る。
Hi Joey,
A1. No, the fail-safe state machine still monitors, counts faults and FLT_ERR_CNT increases as normal, but the deep fail-safe mode is not entered when the fault error counter reaches max value.
A2. No, intermediate will trigger as it configured.
B1. Yes, SPI request will not increase FLT ERR Counter and only fault impact.
B2. Yes, your understanding is correct.
B3. Yes, you are right.
C. Yes.
Best regards,
Tomas
Best regards,
Tomas
Hi Joey,
A1. No, the fail-safe state machine still monitors, counts faults and FLT_ERR_CNT increases as normal, but the deep fail-safe mode is not entered when the fault error counter reaches max value.
A2. No, intermediate will trigger as it configured.
B1. Yes, SPI request will not increase FLT ERR Counter and only fault impact.
B2. Yes, your understanding is correct.
B3. Yes, you are right.
C. Yes.
Best regards,
Tomas
Best regards,
Tomas