Hi,
I have designed a board using P2020 processor,at first the board worked well,but then i changed the hardware design in the 2th edition,i have updated the board using a diffierent CPLD,which provides the power-on logic control.There's no other changes.I found that the processor cannot be in the 'ready' state,it always be in the 'asleep' state.Would you please tell me what i should do next?Thanks very much!
You have to check what is wrong with the CPLD logic.
It is needed to refer to the P2020 QorIQ Integrated Processor Reference Manual, 4.5.2 Power-on reset sequence and P2020 QorIQ Integrated Processor Hardware Specifications, 2.5 RESET Initialization.