TDM UMCC synchronization in transparent mode

[seblol]

Hello,

We are currently writing a driver to operate a T1040 QuiccEngine TDM link with UMCC feature.

This link is supposed to work in transparent mode, and we do not need to use any synchronization pattern.

We have first tried to deactivate the synchronization by setting CHAMR[SYNC] = 0 but the received data are shifted. This is specified in MCC 23.2.2.2 chapter of the QEIWRM. Even if related to the MCC, I suppose this restriction is also applicable to the UMCC.

We have also tried to configure an 8-bit synchronization pattern which works fine for 8-bit time slots, but data in 16-bit time slots is always shifted, even with a 16-bit pattern.

The picture above seems to show a configuration where no pattern is used and data is not shifted (note 3) but the RCVSYNC and ZDSTATE informations are missing...

Could someone please provide us with the missing configuration?

Many thanks,

Sébastien

[Pavel]

Thank you for your feedback.

Have a great day,
Pavel Chubakov

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[seblol]

Hello Pavel,

Thank you for this example.

The issue is solved and the answer was in a previous release of the QEWRM (rev. 4). Unfortunately it was removed from the present release!

It seems that "RCVSYNC = 0xFF7E" is to be set so as to keep data aligned without using the synchronization mechanism.

It now works perfectly for us.

Regards,

Sébastien

[Pavel]

Look at attached file.

It is simple program example for the MPC8560 MCC in transparent mode. Compare this example and your settings.

Have a great day,
Pavel Chubakov

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