P5040DS-PB default RCW hexdump and BootLog RCW does not match

[rammurmu]

I have programmed the default RCW (from ISO V2.0). The boot log RCW dump does not match with that of the default RCW(rcw_26g_2267mhz.bin). Though I understand it adds the preamble ...etc to create the final value of RCW that can be seen on the flash location (0xE8000000) or (0xEC000000) -

BootLog dump of RCW after programming the default RCW bin file (rcw_26g_2267mhz.bin) -

===================================================================

Reset Configuration Word (RCW):
00000000: 0c580000 00000000 22221200 00440000
00000010: 08804400 00283000 fe800000 61000000
00000020: 00000000 00000000 00000000 10070001
00000030: a8000000 00000000 00000000 00000000

===================================================================

hexdump of rcw_26g_2267mhz.bin in host PC ( Little Endian) shows -

===================================================================

0000000 55aa 55aa 0e01 0001 d88c 0000 0000 0000
0000010 a2a2 0092 4400 0000 9c08 0044 2800 0030
0000020 80de 0000 0061 0000 0000 0000 0000 0000
0000030 0000 0000 0710 0000 0000 0000 0000 0000
0000040 0000 0000 0000 0000 0e09 44a0 81d2 0c00
0000050 1308 4080 89f3 ce74
0000058

======================================================================

Is it the same RCW which has been programmed or it is taking the RCW from somewhere else ?

Clarification on this regard would be appreciated.

Regards

Ram

[ufedor]

> I have programmed the default RCW (from ISO V2.0).

How exactly you have done that? Please provide a textual log.

What are settings of the SW1 and SW7 switches?

[rammurmu]

>How exactly you have done that?

Using the JTAG tool.

>Please provide a textual log.

---------------------------------------------------------------------------

U-Boot 2016.012.0+ga9b437f (Nov 07 2016 - 16:03:52 +0530)

CPU0: P5040E, Version: 2.0, (0x820c0020)
Core: e5500, Version: 1.2, (0x80240012)
Clock Configuration:
CPU0:2266.667 MHz, CPU1:2266.667 MHz, CPU2:2266.667 MHz, CPU3:2266.667 MHz,
CCB:800 MHz,
DDR:800 MHz (1600 MT/s data rate) (Asynchronous), LBC:100 MHz
FMAN1: 600 MHz
FMAN2: 600 MHz
QMAN: 400 MHz
PME: 400 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 0c580000 00000000 22221200 00440000
00000010: 08804400 00283000 fe800000 61000000
00000020: 00000000 00000000 00000000 10070001
00000030: a8000000 00000000 00000000 00000000
I2C: ready
Board: P5040DS, Sys ID: 0x20, Sys Ver: 0x02, FPGA Ver: 0x03, vBank: 0
SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz Bank3=125Mhz Bank4=125Mhz
SPI: ready
DRAM: Initializing....using SPD
Detected UDIMM i-DIMM
Detected UDIMM i-DIMM
6 GiB left unmapped
Testing 0x00000000 - 0x7fffffff
Testing 0x80000000 - 0xffffffff
Testing 0x100000000 - 0x17fffffff
Testing 0x180000000 - 0x1ffffffff
Remap DDR 6 GiB left unmapped

8 GiB (DDR3, 64-bit, CL=11, ECC on)
DDR Controller Interleaving Mode: cache line
DDR Chip-Select Interleaving Mode: CS0+CS1
POST memory PASSED
Flash: 128 MiB
L2: 512 KiB enabled
Corenet Platform Cache: 2 MiB enabled
SEC0: RNG instantiated
NAND: 512 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment

EEPROM: CRC mismatch (0ca3851e != ffffffff)
PCIe1: Root Complex, no link, regs @ 0xfe200000
PCIe1: Bus 00 - 00
PCIe2: Root Complex, no link, regs @ 0xfe201000
PCIe2: Bus 01 - 01
PCIe3: disabled
In: serial
Out: serial
Err: serial
Warning: SERDES bank 3 expects reference clock 150MHz, but actual is 125MHz
Net: Initializing Fman
Fman1: Uploading microcode version 106.1.15
Could not get PHY for SUPER_HYDRA_FM1_SGMII_MDIO: addr 28
Failed to connect
Could not get PHY for SUPER_HYDRA_FM1_SGMII_MDIO: addr 29
Failed to connect
Could not get PHY for SUPER_HYDRA_FM1_TGEC_MDIO: addr 0
Failed to connect
Fman2: Uploading microcode version 106.1.15
Could not get PHY for SUPER_HYDRA_FM2_SGMII_MDIO: addr 28
Failed to connect
Could not get PHY for SUPER_HYDRA_FM2_SGMII_MDIO: addr 29
Failed to connect
Could not get PHY for SUPER_HYDRA_FM2_TGEC_MDIO: addr 4
Failed to connect
FM1@DTSEC3
Error: FM1@DTSEC3 address not set.
, FM1@DTSEC4
Error: FM1@DTSEC4 address not set.
, FM1@DTSEC5
Error: FM1@DTSEC5 address not set.
, FM1@TGEC1
Error: FM1@TGEC1 address not set.
, FM2@DTSEC3
Error: FM2@DTSEC3 address not set.
, FM2@DTSEC4
Error: FM2@DTSEC4 address not set.
, FM2@DTSEC5
Error: FM2@DTSEC5 address not set.
, FM2@TGEC1
Error: FM2@TGEC1 address not set.

Hit any key to stop autoboot: 10     0
=>

>What are settings of the SW1 and SW7 switches?

SW1

ON=> 5 , 7

OFF=> 1,2,3,4,6,8

SW6

ON=> 7,8

OFF=> 1,2,3,4,5,6

[ufedor]

> SW1

> ON=> 5 , 7

This means that the RCW source is I2C EEPROM - refer to the P5040 DS Hardware Getting Started, Table 5.

[rammurmu]

>How exactly you have done that?

using the JTAG tool, erasing the flash and programming the binary rcw_26g_2267mhz.bin in the NOR flash (location 0xE8000000 and 0xEC000000)

[addiyi]

Check from where board is booting and also if board is booting from NOR, check from what bank is booting.

Adrian