Hello,
I'm currently trying to calculate the size of the E500MC L1+L2-Caches and the P4080 CPC(L3-Cache) including all of its status, tag, parity, ecc bits and so on. So far I've come up with the following results, but I would love if you guys could run them through, because there are a lot of uncertainties marked with "NOT SURE". I got all my information from the reference manuals of the e500mc and the P4080, but some important parts are missing and I guessed them to my best knowledge.
Thank you in advance and let me know if you need more information.
Best regards,
Mirko
L1-Cache:
Data-Cache:
- 32 KB size
- 8-way set associative
- 64-byte cache blocks/cache line
--> 64 sets of eight blocks
- four state MESI protocol
- lock bit
- cast-out bit
- 1 parity bit per byte
- 1 parity bit per tag
--> (32 * 1024) / 64 = 512 cache lines
Per Cache Line:
--> 64 byte of data = 512 bit
--> 3 Status bit (M, V, and S)
--> 1 lock bit
--> 1 cast-out bit
--> data parity: 64 bit
--> Tag size: 36 bit (NOT SURE)
--> Tag parity: 1 bit
= 512 + 3 + 1 + 1 + 64 + 36 + 1 = 618 bit per cache line
--> 512 lines * 618 = 316416 bit = 39552 Byte = 38.625 KB Cache size
Instruction-Cache:
- 32 KB size
- 8-way set associative
- 64-byte cache blocks/cache line
- Valid/Invalid bit
- lock bit
- 1 parity bit per word
- 1 parity bit per tag
--> (32 * 1024) / 64 = 512 cache lines
Per Cache Line:
--> 64 byte of data = 512 bit
--> 1 Status bit (V)
--> 1 lock bit
--> data parity: 8 bit
--> Tag size: 36 bit (NOT SURE)
--> Tag parity: 1 bit
= 512 + 1 + 1 + 8 + 36 + 1 = 559 bit per cache line
--> 512 lines * 570 = 286208 bit = 35776 Byte = 34.9375 KB Cache size
L2-Cache:
- 128 KB size
- 8-way set associative
- 64-byte cache blocks/cache line
--> 256 sets of 8 blocks
- MESI protocol
- lock bit
- 7-bit pseudo-LRU per set --> 7 * 256 = 1792 bits
- 7 bit data ecc per word (NOT SURE)
- 1 bit data parity per word (NOT SURE)
- 7 bit tag ecc per word (NOT SURE)
- 1 bit tag parity per word (NOT SURE)
--> (128 * 1024) / 64 = 2048 cache lines
Per Cache Line:
--> 64 byte of data = 512 bit
--> 3 Status bit (M, V, and S)
--> 1 lock bit
--> data parity: 16 bit
--> data ecc: 16 * 7 = 112 bit
--> tag parity: 1 bit
--> tag ecc: 7 bit
--> tag size: 36 bit
= 512 + 3 + 1 + 16 + 112 + 1 + 7 + 36 = 688 bit per cache line
--> 2048 lines * 688 + 1792= 1410816 bit = 176352 Byte = 172.21875 KB Cache size
L3-Cache:
2 x CPC
CPC:
- 1 MB size
- 32-way set associative
- 64 byte per cache block/cache line
--> 2048 sets of 8 blocks
- MESI protocol (NOT SURE)
- lock bit
- 7-bit pseudo-LRU per set --> 7 * 2048 = 14336 bits (NOT SURE)
- 8 ecc bits per 64 bits of data
- 7 ecc bits for each 33-bit tag (tag address)
- 5 ecc bits for each 9-bit tag (status bits)
--> (1 * 1024 * 1024) / 64 = 16384 cache lines
Per Cache Line:
--> 64 byte of data = 512 bit
--> Tag address size: 33 bit (NOT SURE)
--> Status size: 9 bit (NOT SURE)
--> data ecc: 8 * 8 = 64 bit
--> tag address ecc: 7 bit
--> status ecc: 5 bit
= 512 + 33 + 9 + 64 + 7 + 5 = 630 bit per cache line
--> 16384 lines * 630 + 14336 = 10336256 bit = 1292032 Byte = 1261.75 KB CPC size
--> 2 * 1261.75 = 2523.5 KB Cache size
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