P2040: eSPI configuration

[gouravjain]

Dear all,

Can any one guide me how to enable SPI interface in uboot for P2040 chipset.

I'm using SDK: QorIQ-SDK-V1.4

Found the file "driver/spi/fsl_espi.c" but seems like its not complete file.

Thanks in advance.

regards,

Gourav jain

[ufedor]

The SPI is enabled in U-Boot by default.

Please note that the SDK V1.4 is an old one and it is recommended to use SDK V1.9.

Which board is in question?

Which RCW is used? - ensure that RCW[SPI]=0

[gouravjain]

Thanks for your reply ..

Our board is based on P2041RDB.

Regarding RCW bits 369-370: 00 i.e SPI_CS enabled.

Uboot log:

U-Boot 2013.01 (Feb 26 2018 - 17:49:13)

CPU0: P2040E, Version: 2.0, (0x82180020)
Core: E500MC, Version: 3.2, (0x80230032)
Clock Configuration:
CPU0:800 MHz, CPU1:800 MHz, CPU2:800 MHz, CPU3:800 MHz,
CCB:400 MHz,
DDR:400 MHz (800 MT/s data rate) (Asynchronous), LBC:50 MHz
FMAN1: 200 MHz
QMAN: 200 MHz
PME: 200 MHz
L1: D-cache 32 kB enabled
I-cache 32 kB enabled
Reset Configuration Word (RCW):
00000000: 4c180000 00000000 58540000 00000000
00000010: 3c8e90c3 e7c02000 de800000 04000000
00000020: 00000000 00000000 00000000 c8198300
00000030: 00000000 00000000 00000000 00000000
HMD Board: P2040,
CYCLONE FPGA version - 2. status 255
PPC Software version - 3. status 255
ETHERNET SWITCH version- 1. status 255
SRIO SWITCH version - 1. status 255
vBank: 0

I2C: ready
SPI: ready
DRAM: Initializing....using SPD
Detected UDIMM HMT451S6AFR8C-PB
2 GiB left unmapped
4 GiB (DDR3, 64-bit, CL=6, ECC off)
Testing 0x00000000 - 0x7fffffff
Testing 0x80000000 - 0xffffffff
Remap DDR 2 GiB left unmapped

POST memory PASSED
Flash: 128 MiB
L2: N/A
Corenet Platform Cache: 1024 KB enabled
Using SERDES configuration 0xf, lane settings:
SERDES: bank 3 disabled
SRIO1: disabled
DUMP BEFORE erratum
SRIO REGDUMP:
pescsr-00030301,edcsr-00000004,iecsr-00000000,ecacsr-00000000
pcseccsr0-00000000,peccsr[0]-00000000,peccsr[1]-00000000,peccsr[2]-00000000
ltledcsr-00000000,ltlaccsr-00000000,ltldidccsr-00000000,ltlcccsr-00000000,slcsr-c0800000
value-602400
conf_lane=0,init_lane=3
unlikely1
clear err**************
unlikely3
SRIO2: enabled but port error
DUMP AFTER erratum
SRIO REGDUMP:
pescsr-00000001,edcsr-00000000,iecsr-00000000,ecacsr-00000000
pcseccsr0-00000000,peccsr[0]-00000000,peccsr[1]-00000000,peccsr[2]-00000000
ltledcsr-00000000,ltlaccsr-00000000,ltldidccsr-00000000,ltlcccsr-00000000,slcsr-c0000000
NAND: 512 MiB
MMC: FSL_SDHC: 0
EEPROM: Invalid ID (ff ff ff ff)
PCIe3: disabled
In: serial
Out: serial
Err: serial

Could you pls let me know the SPI file location so that i can put some prints. As of now i tried "driver/spi/fsl_espi.c"

regards,

Gourav

[ufedor]

How provided log shows that SPI is not operational?

The U-Boot eSPI driver is located at:

http://git.freescale.com/git/cgit.cgi/ppc/sdk/u-boot.git/tree/drivers/spi/fsl_espi.c?id=fsl-sdk-v1.4

[gouravjain]

One more question i wanted to ask, 

Do we need to do entry in dts file, for device those are connected in SPI bus ??

[ufedor]

To test SPI functionality it is possible to use U-Boot "sf" commands.

> Do we need to do entry in dts file, for device those are connected in SPI bus ?

No, only for the eSPI controller itself:

sdk/linux.git - Freescale PowerPC Linux Tree 

sdk/linux.git - Freescale PowerPC Linux Tree 

[gouravjain]

Hi,

Is there any command in linux like "sf" in uboot??

[gouravjain]

Hi,

I didn't say "neither non-operational nor operational". Even i wanted to ask, How to verify whether its working or not? Any print or anything...

Currently, I am preparing BSP for my card which is yet to come.

The location which you have shared redirected to SDK V-1.4 only.  While in above response you suggested to use V-1.9.