P1022 DDR3 Clk Range

[nishad_kamdar]

I am using a Custom board with P1022 Processor on it.

I was going through the P1022DS reference manual which says that the DDR3 Clock is Asynchronous and is set at a frequency of 667MHz.

However, the Design Checklist of P1022 Processor (AN4343 Page 14) says that the maximum frequency for DDR3 Controller is 400MHz.

Could someone explain how will this work?

Is there something i am missing here ? 

[nishad_kamdar]

Ok

Now i get it.

Thanks for the reply.

[hermann_ruckerb]

Hi,

This was a common mistake in the beginning of DDR Memory: Mixing MHz and Mb/s. Frequency need to be given in MHz and Datarate in Mb/s.  I'm a bit surprised to see such a mistake today...

Correct usage would be to give the Clock frequency in MHz, e. g. 400MHz.

The corresponding datarate for the Databus would be 800Mb/s. The maximum Frequency you could see on the Databus is still 400MHz for a clock like 10101 pattern.

The CA bus is still Single Datarate, so for a 400MHz CLK we do have 400Mb/s on the CA bus. The max. Frequency you can see on the CA signal is 200MHz for a 10101 like pattern.

Hermann

[Bulat · Accepted solution]

The P1022DS reference manual refers to the data rate frequency (667MHz), this corresponds to the DDR clock frequency of 333.3 MHz.

The AN4343 explicitly says that the maximum frequency of 400MHz assumes MCK[0:5] clock outputs, this corresponds to the data rate of 800MHz. So there is no contradiction, P1022DS runs DDR3 interface at proper frequency, within specified frequency range.