P1010 SRAM Initialization

[yoavbaryoseph]

Hi,

I am trying to port existing Boot SW into CodeWarrior (developed under OS IDE, currently trying to move into a non-OS platform).

Currently I have only small script configuring the TLBs etc through the last 4k of the flash.

Then I need to configure the IFC controller so can execute from the rest of the flash.This is executed from SRAM, as if it is executed from flash we loose the program flow as ifc settings will cause loosing the flash for a moment.

If can anyone assist me with the following:

1. I found that from an unknown reason there is a failure in copying the function to the SRAM - maybe not initialized properly, although same code is running on different IDE.

2. Another strange issue - is that from the assembly file (entry.s) there is use of macros (#define) from .h files and they are not expanded properly., so I had to write it as is (you can see the macros in comments and the expansion below it).

I have attached:
1. entry.s - the small assembly file mentioned above.

2. .lcf file

3. .h files included (shareAsm includes the macros)

also here are the two functions called:

flashSet which calls csFlash.

void flashSet(void)
{
unsigned int *dst, *src;
int i;

void (*setup_ifc_sram)(void);

unsigned int regTemp;

/*
* Work Around for IFC Erratum A-003549. This issue is P1010
* specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC
* Hence specifically selecting CS3.
*/
regTemp = *((volatile unsigned int *) (CCSBAR + 0xE0060));
regTemp |= MPC85xx_PMUXCR_LCLK_IFC_CS3;
*((volatile unsigned int *) (CCSBAR + 0xE0060)) = regTemp;

/* Copy the code in setup_ifc to L2SRAM. Do a word copy
* because NOR Flash on P1010 does not support byte
* access (Erratum IFC-A002769) */

setup_ifc_sram = (void *) SRAM_ADDR;
dst = (unsigned int *) SRAM_ADDR;
src = (unsigned int *) csFlash;

// Copy csFlash() Code to SRAM and run to enable run it within SRAM
// See .csFlash size at .map file for true number of words to copy
for (i = 0; i < 50; i++)
{
*dst++ = *src++;
}

//__asm__ ( "sync");
__asm__ ( "isync");

setup_ifc_sram();
}

//*** Flash Chip Select Setting. During this function, the Chip Select we are "loose" the Flash until amask updating
//*** So we need to run this code within SRAM area to enable program flow.
void csFlash(void) {
// cspr Reg. Set The value Should be 0x00000101 (NOR Flash (see Prog. Ref 12.3.2 MSEL ) but
// It working only if we set MSEL=10 (GPCM). Probably should be changed for real HW. Boris 19.06.2013
*((volatile unsigned int *) (&IFC_BASE_ADDR[0].cspr_cs[0].cspr)) = (FLASH_BASE_ADRS | 0x00000101);
*((volatile unsigned int *) (&IFC_BASE_ADDR[0].csor_cs[0].csor)) = 0x0000E000; // Shift by 7
*((volatile unsigned int *) (&IFC_BASE_ADDR[0].amask_cs[0].amask)) =0xFC000000; // Address Mask 64Mb See Table 12-11 (FE = 32 MB)
__asm__ ( "isync");

}

Many thanks in advance.

Yoav

[yipingwang]

Hello Yoav Bar Yospeh,

Please refer to the following section to initialize SRAM.

##################################################################################
# configure internal SRAM at 0x00000000

# L2CTL
# bit 0 = 0 - L2E: L2 SRAM disabled
# bit 1 = 1 - L2I: L2 flash invalidate
# bit 2-3 = 01 - L2SIZ: = 256K
# bit 13-15 = 001 - L2SRAM: Entire array as SRAM (256K)
mem [CCSR 0x20000] = 0x50010000

# L2SRBAR0
# bit 0-17 = BASE addr: 0x00000000
mem [CCSR 0x20100] = 0x00000000

# L2SRBAREA0
# bit 28-31 = EXTENTED BASE addr: 0x00000000
mem [CCSR 0x20104] = 0x00000000

# L2CTL
# bit 0 = 1 - L2E: L2 SRAM enable
mem [CCSR 0x20000] = 0x90010000

MMU initialization

# define 256KB TLB entry 3: 0x00000000 - 0x0003FFFF; for internal chip SRAM
reg ${CAM_GROUP}L2MMU_CAM3 = 0x400001C0FC0800000000000000000001

Please refer to Freescale\CW_PA_v10.5.1\PA\PA_Support\Initialization_Files\QorIQ_P1\P1010RDB_init_sram.tcl for details.

For IFC controller configuration, please refer to IFC Controller Configuration on QorIQ Custom Boards.

Thanks,

Yiping

[yoavbaryoseph]

Thanks a lot