Increasing ELBC in P4080DS

[yyurtcan]

Basically, I want to increase elbc clock by increasing sysclk (change SW3 from sysclk= 100 MHz to 133 MHz) however I dont want to violate other system operation. To do that I need to change RCW. I dont know which part I need to change. Could you provide information for that?

Best regards.

[yyurtcan]

Ok. Final question, I have tried SW3 change from 100 to 111 (which is 133 MHz), DDR, CPU, CCB and eLBC change but board could not boot. So if I change  their values in RCW, can the board boot?

[yyurtcan]

If I change SW3 from 100 to 111 Can I get elbc 133 MHz clock?

[ufedor]

NO.

a) LCLK can't be greater than 100MHz - refer to the P4080/P4081 QorIQ Integrated Processor Hardware Specifications, Table 52. Enhanced Local Bus Timing Specifications

[yaseryurtcan]

U-Boot 2016.03 (Apr 07 2016 - 09:51:10 +0300)

CPU0:  P4080E, Version: 3.0, (0x82080030)

Core:  e500mc, Version: 3.1, (0x80230031)

Clock Configuration:

       CPU0:1499.985 MHz, CPU1:1499.985 MHz, CPU2:1499.985 MHz, CPU3:1499.985 MHz,

       CPU4:1499.985 MHz, CPU5:1499.985 MHz, CPU6:1499.985 MHz, CPU7:1499.985 MHz,

       CCB:799.992 MHz,

       DDR:649.994 MHz (1299.987 MT/s data rate) (Asynchronous), LBC:99.999 MHz

       FMAN1: 599.994 MHz

       FMAN2: 599.994 MHz

       QMAN:  399.996 MHz

       PME:   599.994 MHz

L1:    D-cache 32 KiB enabled

       I-cache 32 KiB enabled

Reset Configuration Word (RCW):

       00000000: 105a0000 00000000 1e1e181e 0000cccc

       00000010: 3842440c 3c3c2000 de800000 e1000000

       00000020: 00000000 00000000 00000000 008b6000

       00000030: 00000000 00000000 00000000 00000000

Board: P4080DS, Sys ID: 0x17, Sys Ver: 0x01, FPGA Ver: 0x0c, vBank: 0

SERDES Reference Clocks: Bank1=100MHz Bank2=125MHz Bank3=125MHz

I2C:   ready

SPI:   ready

DRAM:  Initializing....using SPD

Detected UDIMM i-DIMM

Detected UDIMM i-DIMM

2 GiB left unmapped

Testing 0x00000000 - 0x7fffffff

Testing 0x80000000 - 0xffffffff

Remap DDR 2 GiB left unmapped

4 GiB (DDR3, 64-bit, CL=9, ECC on)

       DDR Controller Interleaving Mode: cache line

       DDR Chip-Select Interleaving Mode: CS0+CS1

POST memory PASSED

Flash: 128 MiB

L2:    128 KiB enabled

Corenet Platform Cache: 2 MiB enabled

SRIO1: disabled

SRIO2: disabled

MMC:   FSL_SDHC: 0

EEPROM: CRC mismatch (707eb693 != ffffffff)

PCIe1: Root Complex, x1 gen1, regs @ 0xfe200000

  01:00.0     - 104c:8241 - Serial bus controller

PCIe1: Bus 00 - 01

PCIe2: disabled

PCIe3: Root Complex, x1 gen1, regs @ 0xfe202000

  03:00.0     - 1095:3132 - Mass storage controller

PCIe3: Bus 02 - 03

In:    serial

Out:   serial

Err:   serial

Net:   Fman1: Uploading microcode version 106.2.14

Could not get PHY for P4080DS_MDIO3: addr 4

Failed to connect

Fman2: Uploading microcode version 106.2.14

Could not get PHY for P4080DS_MDIO8: addr 30

Failed to connect

Could not get PHY for P4080DS_MDIO8: addr 31

Failed to connect

Could not get PHY for P4080DS_MDIO1: addr 0

Failed to connect

FM1@DTSEC2 [PRIME], FM1@TGEC1, FM2@DTSEC3, FM2@DTSEC4, FM2@TGEC1

Hit any key to stop autoboot:  0

=>

Please find the output of uboot above. SW3 settings default. I want to maksimum elbc (133 MHz) clock. I tihnk I need change SW3 and RCW. Could you also provide new RCW for that?

Best regards.

[ufedor]

It was written:

"a) LCLK can't be greater than 100MHz"

in the provided log:

"LBC:99.999 MHz"

The eLBC clock is already at its maximum.

[ufedor]

Please provide additional information:

1) current U-Boot output

2) desired eLBC clock frequency

Note that:

a) LCLK can't be greater than 100MHz - refer to the P4080/P4081 QorIQ Integrated Processor Hardware Specifications, Table 52. Enhanced Local Bus Timing Specifications

b) maximum LCLK frequency is equal to (Platform Clock) / 8

For the processor clocking details please refer to the P4080 QorIQ Multicore Communication Processor Reference Manual, 4.6.5 Clocking.