Background:
I'm working on the 33772C chip and it seems to be working at the system level with an NXP microcontroller over TPL.
I'm digging deeper and wanting to understand what is being communicated across TPL.
I see that CRC calcs are part of the communication frames and figured this was a great way to establish endianness and confirm I'm understanding bus data correctly.
I can plug the 5 bytes in the 33772C data sheet CRC example in and get the correct CRC with an online calc.
My Struggle:
If I plug in data off the bus (via the Saleae logic analyzer) - bad CRC result.
My Question:
Can you advise on what I need to change to make sense of the CRC as viewed with the TPL sniffer?
