SJA1110 no communication 100Base-T1 to 100Base-TX

[Debelak]

Hello,

We are using the SJA1110C variant with an 100 Base-TX interface on port 1 and an 100 Base-T1 interface on port 5. We have successfully configured the Switch core via SPI_AP based on a modified .hex file generated from the SJA evaluation board configuration tools python scripts.

We are trying to establish a communication between those ports using a vector VN5620 network interface. Both the vector interface and the SJA1110C show link up and correct speed on both ports.

We try to send UDP packages from one port to the other, but no packets are received. The switch registers MAC_DIAG_CNTRS_FLGS, HIGH_LVL_DIAG_1 and IP_PROT_STATS show no activity, e.g. no counters are incremented.

In summary: the switch config is accepted, both PHY’s are enabled and configured, both ports show link up, but there is no communication possible.

Is there something in switch core config or phy config we are missing?

Thank you for your help

[RKS1110]

Hi,

I have the same problem. Link on 100BASE-TX is up but no flow to port 1 or the other ports of the switch.

Any hint is welcome.

Best regards, Rainer

[RKS1110]

The problem has been solved by loading the correct configuration into the switch via SPI.

With SJA1110 SDK and S32 Design Studio one can create via configuration tool of the IDE a .mex file for the SJA1110. See "Switch Table Configuration" in the "switch_x" part.

I do not know if it is necessary to configure L2 forwarding (L2 -> L2 Forwarding table port), but I did it this way that every port forwards to every other but not the port itself.

[Debelak]

Hello Lukas,

Thanks for the answer.

We used the sample script attached Our component is the SJA1110C.

Thanks and Greetings

Albrecht

[lukaszadrapa]

1. Could you read out the CFG_STAT register bit 31(CONFIGSDONE), to ensure that a valid config was loaded?
2. In general the configuration seems OK.
3. I assume that you are using a custom board. Is it possible to share the schematic for review?
Regards,
Lukas

[Debelak]

Hello Lukas,

the CONFIGDONE bit is set, also the N_DEVICE_CFG pin indicates the configuration is done.

Yes, we have a custom design, unfortunately we cannot share the schematics.

Could you provide detailed procedure to enable the 100BT1 PHY and 100BTX PHY?

In the example scripts and SDK’s we found that in the process of activating the 100BTX PHY some undocumented registers are written with undocumented values and purpose.

Also we don’t have a software running on the MCSS but disabled the Watchdog clock source (OUTCLK_7_C) so the device doesn’t reset.

Our current configuration process for 100BTX PHY is:

Register	Register Name	Read/ Write	Value	Comment
0x60h	POWER_DOWN_CONTROL	W	0x60h	Disable True Power Down Mode
0x00h	BASIC_CONTROL_REGISTER	W	0x8000h	Soft Reset
0x00h		R	while bit15==1	Wait until reset done
0x70h	SPECIAL_INTERNAL_TEST_CONTROLS	W	0x1600h	Disable DSP/AFE register reset
0x44h	MODE_CONTROL_STATUS	W	0x40h	Disable auto-mdix and configure  MDIX mode
0x00h	BASIC_CONTROL_REGISTER	W	0x2100h	SPEED100M, Full Duplex

Our current configuration process for 100BT1PHY is:

Pin PHY_AUTO_MODE = 1

Pin PHY_AUTO_POL_DET = 1

Pin PHY_M_S5 = 1

Register	Register Name	Read/ Write	Value	Comment
((30d & 0x1f) << 0) | ((1d & 0x7) << 7) | ((0 & 3) << 5)	Clause45 Addressing for Register 101h	W	0x101h &= 0xffffh	MMD30: PHY_1_CONFIG Read access
((30d & 0x1f) << 0) | ((1d & 0x7) << 7) | ((2 & 3) << 5)		R	GCR Content	Read current content and remember
((30d & 0x1f) << 0) | ((1d & 0x7) << 7) | ((0 & 3) << 5)		W	0x101h &= 0xffffh	MMD30: PHY_1_CONFIG Read access
((30d & 0x1f) << 0) | ((1d & 0x7) << 7) | ((2 & 3) << 5)		W	GCR Content |= (1 << 14)	Set Enable bit

Best regards

Albrecht Debelak

[lukaszadrapa]

Hi @Debelak 

which sample script did you use and how did you update it? Can you share it?

Regards,

Lukas