LS1028A JTAG Connectivity

[Sathian]

We have custom based LS1028A board and trying to halt the processor via JTAG. 

We could able to do "halt" in EVM(Attached image) but not in custom board, What could be the problem and solution ?

[ufedor]

Which exactly DUT board is in question?

Is POR behaviour of the reset signals on the DUT board similar to shown in the "Figure 6. Power-On Reset Sequence" in the QorIQ LS1028A Reference Manual?

Is the DUT board capable to boot?

Please confirm that JTAG interface is implemented as described in the AN12028 - QorIQ LS1028A Design Checklist, 5.20 JTAG pin termination recommendations.

Is TRST_B asserted during power-on reset flow?